106 lines
3.5 KiB
Tcl
106 lines
3.5 KiB
Tcl
###############################################################################
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## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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# ip
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
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global VIVADO_IP_LIBRARY
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adi_ip_create axi_ad7606x
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adi_ip_files axi_ad7606 [list \
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"$ad_hdl_dir/library/common/ad_edge_detect.v" \
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"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
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"$ad_hdl_dir/library/common/ad_rst.v" \
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"$ad_hdl_dir/library/common/up_axi.v" \
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"$ad_hdl_dir/library/xilinx/common/ad_dcfilter.v" \
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"$ad_hdl_dir/library/common/ad_datafmt.v" \
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"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
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"$ad_hdl_dir/library/common/up_xfer_status.v" \
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"$ad_hdl_dir/library/common/up_clock_mon.v" \
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"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
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"$ad_hdl_dir/library/common/up_adc_channel.v" \
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"$ad_hdl_dir/library/common/up_adc_common.v" \
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"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
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"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
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"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
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"$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
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"axi_ad7606x_16b_pif.v" \
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"axi_ad7606x_18b_pif.v" \
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"axi_ad7606x.v" ]
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adi_ip_properties axi_ad7606x
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set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_ad7606x} [ipx::current_core]
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ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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set reset_intf [ipx::infer_bus_interface adc_reset xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]]
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set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_intf]
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set_property value "ACTIVE_HIGH" $reset_polarity
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set cc [ipx::current_core]
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set_property display_name "AXI AD7606X" $cc
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set_property description "AXI AD7606X HDL interface" $cc
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## define external_clk port as clock interface
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adi_add_bus external_clk slave \
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"xilinx.com:signal:clock_rtl:1.0" \
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"xilinx.com:signal:clock:1.0" \
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[list {"external_clk" "CLK"} ]
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adi_set_ports_dependency "external_clk" \
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"(spirit:decode(id('MODELPARAM_VALUE.EXTERNAL_CLK')) = 1)" 0
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## parameter validation
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set_property -dict [list \
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"value_format" "bool" \
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"value" "true" \
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] \
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[ipx::get_hdl_parameters EXTERNAL_CLK -of_objects $cc]
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## customize XGUI layout
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## remove the automatically generated GUI page
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ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc]
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ipx::save_core $cc
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## create a new GUI page
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ipgui::add_page -name {AXI AD7606X} -component $cc -display_name {AXI AD7606X}
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set page0 [ipgui::get_pagespec -name "AXI AD7606X" -component $cc]
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ipgui::add_param -name "EXTERNAL_CLK" -component $cc -parent $page0
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set_property -dict [list \
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"display_name" "EXTERNAL_CLK" \
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"tooltip" "External clock for the ADC" \
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"widget" "checkBox" \
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] [ipgui::get_guiparamspec -name "EXTERNAL_CLK" -component $cc]
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ipgui::add_param -name "DEV_CONFIG" -component $cc -parent $page0
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set_property -dict [list \
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"widget" "comboBox" \
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"display_name" "Device Type Selection" \
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] [ipgui::get_guiparamspec -name "DEV_CONFIG" -component $cc]
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set_property -dict [list \
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"value_validation_type" "pairs" \
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"value_validation_pairs" { \
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"AD7606B" "0" \
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"AD7606C-16" "1" \
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"AD7606C-18" "2" \
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} \
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] [ipx::get_user_parameters DEV_CONFIG -of_objects $cc]
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adi_add_auto_fpga_spec_params
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## save the modifications
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ipx::create_xgui_files $cc
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ipx::save_core $cc
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