50 lines
1.5 KiB
Tcl
50 lines
1.5 KiB
Tcl
###############################################################################
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## Copyright (C) 2021 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIJESD204
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###############################################################################
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proc init {cellpath otherInfo} {
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set ip [get_bd_cells $cellpath]
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bd::mark_propagate_override $ip \
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"ASYNC_CLK"
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}
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proc detect_async_clk { cellpath ip param_name clk_a clk_b } {
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set param_src [get_property "CONFIG.$param_name.VALUE_SRC" $ip]
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if {[string equal $param_src "USER"]} {
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return;
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}
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set clk_domain_a [get_property CONFIG.CLK_DOMAIN $clk_a]
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set clk_domain_b [get_property CONFIG.CLK_DOMAIN $clk_b]
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set clk_freq_a [get_property CONFIG.FREQ_HZ $clk_a]
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set clk_freq_b [get_property CONFIG.FREQ_HZ $clk_b]
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set clk_phase_a [get_property CONFIG.PHASE $clk_a]
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set clk_phase_b [get_property CONFIG.PHASE $clk_b]
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# Only mark it as sync if we can make sure that it is sync, if the
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# relationship of the clocks is unknown mark it as async
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if {$clk_domain_a != {} && $clk_domain_b != {} && \
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$clk_domain_a == $clk_domain_b && $clk_freq_a == $clk_freq_b && \
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$clk_phase_a == $clk_phase_b} {
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set clk_async 0
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} else {
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set clk_async 1
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}
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set_property "CONFIG.$param_name" $clk_async $ip
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}
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proc propagate {cellpath otherinfo} {
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set ip [get_bd_cells $cellpath]
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set link_clk [get_bd_pins "$ip/clk"]
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set device_clk [get_bd_pins "$ip/device_clk"]
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detect_async_clk $cellpath $ip "ASYNC_CLK" $link_clk $device_clk
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}
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