142 lines
4.1 KiB
Tcl
142 lines
4.1 KiB
Tcl
###############################################################################
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## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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# adi_intel_device_info_enc.tcl
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# The main rule when adding a new parameter is to have the same names for the parameter
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# and it's list (valid range type or supported entity and its encoded value type)
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variable auto_set_param_list
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variable fpga_technology_list
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variable fpga_technology
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variable fpga_family_list
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variable fpga_family
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variable speed_grade_list
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variable speed_grade
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variable dev_package_list
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variable dev_package
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variable xcvr_type_list
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variable xcvr_type
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variable fpga_voltage_list
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variable fpga_voltage
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# Parameter list for automatic assignament(generation)
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set auto_gen_param_list { \
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FPGA_TECHNOLOGY \
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FPGA_FAMILY \
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SPEED_GRADE \
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DEV_PACKAGE}
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set auto_set_param_list { \
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FPGA_VOLTAGE \
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XCVR_TYPE}
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# List for automatically assigned parameter values and encoded values
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# The list name must be the parameter name (lowercase), appending "_list" to it
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set fpga_technology_list { \
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{ Unknown 100 } \
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{ "Cyclone V" 101 } \
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{ "Cyclone 10" 102 } \
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{ "Arria 10" 103 } \
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{ "Stratix 10" 104 }}
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set fpga_family_list { \
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{ Unknown 0 } \
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{ SX 1 } \
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{ GX 2 } \
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{ GT 3 } \
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{ GZ 4 } \
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{ "SE Base" 5 }}
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#technology 5 generation
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# family Arria SX
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set speed_grade_list { \
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{ Unknown 0 } \
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{ 1 1 } \
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{ 2 2 } \
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{ 3 3 } \
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{ 4 4 } \
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{ 5 5 } \
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{ 6 6 } \
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{ 7 7 } \
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{ 8 8 }}
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set dev_package_list { \
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{ Unknown 0 } \
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{ BGA 1 } \
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{ PGA 2 } \
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{ FBGA 3 } \
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{ HBGA 4 } \
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{ PDIP 5 } \
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{ EQFP 6 } \
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{ PLCC 7 } \
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{ PQFP 8 } \
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{ RQFP 9 } \
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{ TQFP 10 } \
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{ UBGA 11 } \
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{ UFBGA 12 } \
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{ MBGA 13 }}
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# Ball-Grid Array (BGA)
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# Ceramic Pin-Grid Array (PGA)
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# FineLine BGA (FBGA)
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# Hybrid FineLine BGA (HBGA)
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# Plastic Dual In-Line Package (PDIP)
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# Plastic Enhanced Quad Flat Pack (EQFP)
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# Plastic J-Lead Chip Carrier (PLCC)
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# Plastic Quad Flat Pack (PQFP)
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# Power Quad Flat Pack (RQFP)
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# Thin Quad Flat Pack (TQFP)
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# Ultra FineLine BGA (UBGA-UFBGA)
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# transceiver speedgrade
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set xcvr_type_list { 0 9 }
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set fpga_voltage_list { 0 5000 } ;# min 0mV max 5V
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################################################################################
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proc get_part_param {} {
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global fpga_technology
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global fpga_family
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global speed_grade
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global dev_package
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global xcvr_type
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global fpga_voltage
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set device [get_parameter_value DEVICE]
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# user and system values (sys_val)
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if {[catch {set fpga_technology [quartus::device::get_part_info -family $device]} fid]} {
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set fpga_technology "Unknown"
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}
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if {[catch {set fpga_family [quartus::device::get_part_info -family_variant $device]} fid]} {
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set fpga_family "Unknown"
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}
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if {[catch {set speed_grade [quartus::device::get_part_info -speed_grade $device]} fid]} {
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set speed_grade "Unknown"
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}
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if {[catch {set dev_package [quartus::device::get_part_info -package $device]} fid]} {
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set dev_package "Unknown"
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}
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if {[catch {set xcvr_type [quartus::device::get_part_info -hssi_speed_grade $device]} fid]} {
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set xcvr_type "Unknown"
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}
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if {[catch {set fpga_voltage [quartus::device::get_part_info -default_voltage $device]} fid]} {
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set fpga_voltage "0"
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}
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# user and system values (sys_val)
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regsub {V} $fpga_voltage "" fpga_voltage
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set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val)
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}
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## ***************************************************************************
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## ***************************************************************************
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