Istvan Csomortani b2d86bab47 util_axis_fifo: Fix the FIFO level generation in ASYNC mode ... The FIFO functions in 'first fall through' mode, adjust the fifo level generation so it take into account the valid data which sits on the bus, waiting for ready, too.		2019-01-29 11:38:28 +02:00
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Makefile	Move Altera IP core dependency tracking to library Makefiles	2018-04-11 15:09:54 +03:00
address_gray.v	Add missing timescale annotations	2018-10-17 10:32:47 +03:00
address_gray_pipelined.v	Add missing timescale annotations	2018-10-17 10:32:47 +03:00
address_sync.v	Add missing timescale annotations	2018-10-17 10:32:47 +03:00
util_axis_fifo.v	util_axis_fifo: Fix the FIFO level generation in ASYNC mode	2019-01-29 11:38:28 +02:00
util_axis_fifo_ip.tcl	util_axis_fifo: instantiate block ram in async mode	2018-04-11 15:09:54 +03:00