Adrian Costina 3f2c885189 axi_logic_analyzer: Update triggering delay mechanism		2017-06-08 12:01:49 +03:00
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Makefile	axi_logic_analyzer: Initial commit	2017-01-31 16:23:56 +02:00
axi_logic_analyzer.v	axi_logic_analyzer: Update triggering delay mechanism	2017-06-08 12:01:49 +03:00
axi_logic_analyzer_constr.xdc	axi_logic_analyzer: Switched from BUFGMUX to BUFGMUX_CTRL for glitch free clock switching	2017-02-27 14:19:54 +02:00
axi_logic_analyzer_ip.tcl	library: Delete all adi_ip_constraint process call	2017-04-06 12:36:47 +03:00
axi_logic_analyzer_reg.v	axi_logic_analyzer: Added trigger delay register, renamed fifo depth register	2017-06-06 15:37:00 +03:00
axi_logic_analyzer_trigger.v	license: Add some clarification to the header license	2017-05-31 18:18:56 +03:00