171 lines
7.8 KiB
Tcl
171 lines
7.8 KiB
Tcl
# adc peripherals
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ad_ip_instance util_adxcvr util_fmcadc5_0_xcvr
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ad_ip_parameter util_fmcadc5_0_xcvr CONFIG.QPLL_FBDIV "0010000000"
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ad_ip_parameter util_fmcadc5_0_xcvr CONFIG.CPLL_FBDIV 1
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ad_ip_parameter util_fmcadc5_0_xcvr CONFIG.TX_NUM_OF_LANES 0
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ad_ip_parameter util_fmcadc5_0_xcvr CONFIG.TX_OUT_DIV 2
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ad_ip_parameter util_fmcadc5_0_xcvr CONFIG.TX_CLK25_DIV 10
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ad_ip_parameter util_fmcadc5_0_xcvr CONFIG.RX_NUM_OF_LANES 8
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ad_ip_parameter util_fmcadc5_0_xcvr CONFIG.RX_OUT_DIV 1
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ad_ip_parameter util_fmcadc5_0_xcvr CONFIG.RX_CLK25_DIV 25
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ad_ip_parameter util_fmcadc5_0_xcvr CONFIG.RX_DFE_LPM_CFG 0x0954
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ad_ip_parameter util_fmcadc5_0_xcvr CONFIG.RX_CDR_CFG 0x03000023ff20400020
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ad_ip_parameter util_fmcadc5_0_xcvr CONFIG.RX_PMA_CFG 0x00018480
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ad_ip_instance util_adxcvr util_fmcadc5_1_xcvr
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ad_ip_parameter util_fmcadc5_1_xcvr CONFIG.QPLL_FBDIV "0010000000"
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ad_ip_parameter util_fmcadc5_1_xcvr CONFIG.CPLL_FBDIV 1
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ad_ip_parameter util_fmcadc5_1_xcvr CONFIG.TX_NUM_OF_LANES 0
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ad_ip_parameter util_fmcadc5_1_xcvr CONFIG.TX_OUT_DIV 2
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ad_ip_parameter util_fmcadc5_1_xcvr CONFIG.TX_CLK25_DIV 10
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ad_ip_parameter util_fmcadc5_1_xcvr CONFIG.RX_NUM_OF_LANES 8
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ad_ip_parameter util_fmcadc5_1_xcvr CONFIG.RX_OUT_DIV 1
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ad_ip_parameter util_fmcadc5_1_xcvr CONFIG.RX_CLK25_DIV 25
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ad_ip_parameter util_fmcadc5_1_xcvr CONFIG.RX_DFE_LPM_CFG 0x0954
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ad_ip_parameter util_fmcadc5_1_xcvr CONFIG.RX_CDR_CFG 0x03000023ff20400020
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ad_ip_parameter util_fmcadc5_1_xcvr CONFIG.RX_PMA_CFG 0x00018480
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ad_ip_instance axi_adxcvr axi_ad9625_0_xcvr
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ad_ip_parameter axi_ad9625_0_xcvr CONFIG.NUM_OF_LANES 8
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ad_ip_parameter axi_ad9625_0_xcvr CONFIG.QPLL_ENABLE 0
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ad_ip_parameter axi_ad9625_0_xcvr CONFIG.TX_OR_RX_N 0
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ad_ip_parameter axi_ad9625_0_xcvr CONFIG.LPM_OR_DFE_N 0
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ad_ip_parameter axi_ad9625_0_xcvr CONFIG.SYS_CLK_SEL "00"
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ad_ip_parameter axi_ad9625_0_xcvr CONFIG.OUT_CLK_SEL "010"
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ad_ip_instance axi_adxcvr axi_ad9625_1_xcvr
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ad_ip_parameter axi_ad9625_1_xcvr CONFIG.NUM_OF_LANES 8
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ad_ip_parameter axi_ad9625_1_xcvr CONFIG.QPLL_ENABLE 0
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ad_ip_parameter axi_ad9625_1_xcvr CONFIG.TX_OR_RX_N 0
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ad_ip_parameter axi_ad9625_1_xcvr CONFIG.LPM_OR_DFE_N 0
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ad_ip_parameter axi_ad9625_1_xcvr CONFIG.SYS_CLK_SEL "00"
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ad_ip_parameter axi_ad9625_1_xcvr CONFIG.OUT_CLK_SEL "010"
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ad_ip_instance jesd204 axi_ad9625_0_jesd
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ad_ip_parameter axi_ad9625_0_jesd CONFIG.C_NODE_IS_TRANSMIT 0
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ad_ip_parameter axi_ad9625_0_jesd CONFIG.C_LANES 8
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ad_ip_instance jesd204 axi_ad9625_1_jesd
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ad_ip_parameter axi_ad9625_1_jesd CONFIG.C_NODE_IS_TRANSMIT 0
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ad_ip_parameter axi_ad9625_1_jesd CONFIG.C_LANES 8
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ad_ip_instance axi_ad9625 axi_ad9625_0_core
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ad_ip_parameter axi_ad9625_0_core CONFIG.ID 0
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ad_ip_instance axi_ad9625 axi_ad9625_1_core
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ad_ip_parameter axi_ad9625_1_core CONFIG.ID 1
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ad_ip_instance util_cpack util_ad9625_cpack
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ad_ip_parameter util_ad9625_cpack CONFIG.CHANNEL_DATA_WIDTH 256
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ad_ip_parameter util_ad9625_cpack CONFIG.NUM_OF_CHANNELS 2
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ad_ip_instance axi_dmac axi_ad9625_dma
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ad_ip_parameter axi_ad9625_dma CONFIG.DMA_TYPE_SRC 1
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ad_ip_parameter axi_ad9625_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_ad9625_dma CONFIG.ID 0
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ad_ip_parameter axi_ad9625_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_ad9625_dma CONFIG.AXI_SLICE_DEST 0
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ad_ip_parameter axi_ad9625_dma CONFIG.SYNC_TRANSFER_START 0
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ad_ip_parameter axi_ad9625_dma CONFIG.DMA_LENGTH_WIDTH 24
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ad_ip_parameter axi_ad9625_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_ad9625_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_ad9625_dma CONFIG.DMA_DATA_WIDTH_SRC 64
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ad_ip_parameter axi_ad9625_dma CONFIG.DMA_DATA_WIDTH_DEST 64
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# reference clocks & resets
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create_bd_port -dir I rx_ref_clk_0
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create_bd_port -dir I rx_ref_clk_1
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ad_xcvrpll rx_ref_clk_0 util_fmcadc5_0_xcvr/qpll_ref_clk_*
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ad_xcvrpll rx_ref_clk_0 util_fmcadc5_0_xcvr/cpll_ref_clk_*
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ad_xcvrpll axi_ad9625_0_xcvr/up_pll_rst util_fmcadc5_0_xcvr/up_qpll_rst_*
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ad_xcvrpll axi_ad9625_0_xcvr/up_pll_rst util_fmcadc5_0_xcvr/up_cpll_rst_*
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ad_xcvrpll rx_ref_clk_1 util_fmcadc5_1_xcvr/qpll_ref_clk_*
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ad_xcvrpll rx_ref_clk_1 util_fmcadc5_1_xcvr/cpll_ref_clk_*
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ad_xcvrpll axi_ad9625_1_xcvr/up_pll_rst util_fmcadc5_1_xcvr/up_qpll_rst_*
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ad_xcvrpll axi_ad9625_1_xcvr/up_pll_rst util_fmcadc5_1_xcvr/up_cpll_rst_*
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ad_connect sys_cpu_resetn util_fmcadc5_0_xcvr/up_rstn
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ad_connect sys_cpu_resetn util_fmcadc5_1_xcvr/up_rstn
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ad_connect sys_cpu_clk util_fmcadc5_0_xcvr/up_clk
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ad_connect sys_cpu_clk util_fmcadc5_1_xcvr/up_clk
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# connections (adc)
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ad_xcvrcon util_fmcadc5_0_xcvr axi_ad9625_0_xcvr axi_ad9625_0_jesd
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ad_xcvrcon util_fmcadc5_1_xcvr axi_ad9625_1_xcvr axi_ad9625_1_jesd
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delete_bd_objs [get_bd_nets -of_objects [get_bd_pins util_fmcadc5_1_xcvr/rx_out_clk_0]]
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delete_bd_objs [get_bd_nets -of_objects [get_bd_pins axi_ad9625_1_jesd_rstgen/peripheral_reset]]
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delete_bd_objs [get_bd_cells axi_ad9625_1_jesd_rstgen]
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ad_xcvrpll util_fmcadc5_0_xcvr/rx_out_clk_0 util_fmcadc5_1_xcvr/rx_clk_*
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ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 axi_ad9625_1_jesd/rx_core_clk
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ad_connect axi_ad9625_0_jesd_rstgen/peripheral_reset axi_ad9625_1_jesd/rx_reset
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ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 axi_ad9625_0_core/rx_clk
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ad_connect axi_ad9625_0_jesd/rx_start_of_frame axi_ad9625_0_core/rx_sof
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ad_connect axi_ad9625_0_jesd/rx_tdata axi_ad9625_0_core/rx_data
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ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 axi_ad9625_1_core/rx_clk
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ad_connect axi_ad9625_0_jesd/rx_start_of_frame axi_ad9625_1_core/rx_sof
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ad_connect axi_ad9625_1_jesd/rx_tdata axi_ad9625_1_core/rx_data
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ad_connect axi_ad9625_0_core/adc_raddr_out axi_ad9625_0_core/adc_raddr_in
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ad_connect axi_ad9625_0_core/adc_raddr_out axi_ad9625_1_core/adc_raddr_in
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ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 util_ad9625_cpack/adc_clk
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ad_connect axi_ad9625_0_jesd_rstgen/peripheral_reset util_ad9625_cpack/adc_rst
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ad_connect axi_ad9625_0_core/adc_enable util_ad9625_cpack/adc_enable_0
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ad_connect axi_ad9625_0_core/adc_valid util_ad9625_cpack/adc_valid_0
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ad_connect axi_ad9625_0_core/adc_data util_ad9625_cpack/adc_data_0
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ad_connect axi_ad9625_1_core/adc_enable util_ad9625_cpack/adc_enable_1
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ad_connect axi_ad9625_1_core/adc_valid util_ad9625_cpack/adc_valid_1
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ad_connect axi_ad9625_1_core/adc_data util_ad9625_cpack/adc_data_1
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ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 axi_ad9625_fifo/adc_clk
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ad_connect axi_ad9625_0_jesd_rstgen/peripheral_reset axi_ad9625_fifo/adc_rst
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ad_connect util_ad9625_cpack/adc_valid axi_ad9625_fifo/adc_wr
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ad_connect util_ad9625_cpack/adc_data axi_ad9625_fifo/adc_wdata
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ad_connect axi_ad9625_fifo/adc_wovf axi_ad9625_0_core/adc_dovf
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ad_connect axi_ad9625_fifo/adc_wovf axi_ad9625_1_core/adc_dovf
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ad_connect sys_cpu_clk axi_ad9625_fifo/dma_clk
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ad_connect sys_cpu_clk axi_ad9625_dma/s_axis_aclk
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ad_connect sys_cpu_resetn axi_ad9625_dma/m_dest_axi_aresetn
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ad_connect axi_ad9625_fifo/dma_wr axi_ad9625_dma/s_axis_valid
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ad_connect axi_ad9625_fifo/dma_wdata axi_ad9625_dma/s_axis_data
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ad_connect axi_ad9625_fifo/dma_wready axi_ad9625_dma/s_axis_ready
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ad_connect axi_ad9625_fifo/dma_xfer_req axi_ad9625_dma/s_axis_xfer_req
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# interconnect (cpu)
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ad_cpu_interconnect 0x44a60000 axi_ad9625_0_xcvr
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ad_cpu_interconnect 0x44b60000 axi_ad9625_1_xcvr
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ad_cpu_interconnect 0x44a10000 axi_ad9625_0_core
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ad_cpu_interconnect 0x44b10000 axi_ad9625_1_core
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ad_cpu_interconnect 0x44a91000 axi_ad9625_0_jesd
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ad_cpu_interconnect 0x44b91000 axi_ad9625_1_jesd
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ad_cpu_interconnect 0x7c420000 axi_ad9625_dma
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# interconnect (gt/adc)
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ad_mem_hp0_interconnect sys_cpu_clk axi_ad9625_0_xcvr/m_axi
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ad_mem_hp0_interconnect sys_cpu_clk axi_ad9625_1_xcvr/m_axi
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ad_mem_hp0_interconnect sys_cpu_clk axi_ad9625_dma/m_dest_axi
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# interrupts
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ad_cpu_interrupt ps-12 mb-12 axi_ad9625_dma/irq
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# sync
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create_bd_port -dir O rx_clk
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create_bd_port -dir O up_clk
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create_bd_port -dir O up_rstn
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create_bd_port -dir O delay_clk
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create_bd_port -dir O delay_rst
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ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 rx_clk
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ad_connect sys_cpu_clk up_clk
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ad_connect sys_cpu_resetn up_rstn
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ad_connect sys_200m_clk delay_clk
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ad_connect sys_cpu_reset delay_rst
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