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Lars-Peter Clausen de0edc2083 axi_dmac: src_fifo_inf: Clear pipeline when no transfers are active 
Clear the pipeline when no transfers are active to make sure that we do not
get residual data on the first sample for the next transfer.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2014-09-16 21:02:05 +02:00
library axi_dmac: src_fifo_inf: Clear pipeline when no transfers are active 2014-09-16 21:02:05 +02:00
projects projects/common/vc707/vc707_system_bd: AD9625_FMC update to 2014.2 2014-09-16 14:59:36 +02:00
.gitignore a5soc: increase pipeline for qsys 2014-05-04 10:38:53 -04:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
README.md Add a link to EngineerZone 2014-04-15 10:25:18 +03:00

README.md

hdl

Analog Devices HDL libraries and projects

First time users, it is highly recommended to go through our HDL user guide at the following url:

http://wiki.analog.com/resources/fpga/docs/hdl

For support please visit our FPGA Reference Designs Support Community on EngineerZone:

http://ez.analog.com/community/fpga