133 lines
6.0 KiB
Tcl
133 lines
6.0 KiB
Tcl
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package require -exact qsys 13.0
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source ../scripts/adi_env.tcl
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set_module_property NAME axi_ad9671
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set_module_property DESCRIPTION "AXI AD9671 Interface"
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set_module_property VERSION 1.0
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set_module_property DISPLAY_NAME axi_ad9671
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# files
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add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
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set_fileset_property quartus_synth TOP_LEVEL axi_ad9671_alt
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add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/altera/ad_rst.v
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add_fileset_file ad_pnmon.v VERILOG PATH $ad_hdl_dir/library/common/ad_pnmon.v
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add_fileset_file ad_datafmt.v VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v
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add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
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add_fileset_file up_xfer_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_cntrl.v
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add_fileset_file up_xfer_status.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_status.v
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add_fileset_file up_clock_mon.v VERILOG PATH $ad_hdl_dir/library/common/up_clock_mon.v
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add_fileset_file up_drp_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_drp_cntrl.v
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add_fileset_file up_delay_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_delay_cntrl.v
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add_fileset_file up_adc_common.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_common.v
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add_fileset_file up_adc_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_channel.v
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add_fileset_file axi_ad9671_pnmon.v VERILOG PATH axi_ad9671_pnmon.v
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add_fileset_file axi_ad9671_if.v VERILOG PATH axi_ad9671_if.v
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add_fileset_file axi_ad9671_channel.v VERILOG PATH axi_ad9671_channel.v
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add_fileset_file axi_ad9671.v VERILOG PATH axi_ad9671.v
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add_fileset_file axi_ad9671_alt.v VERILOG PATH axi_ad9671_alt.v TOP_LEVEL_FILE
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# parameters
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add_parameter PCORE_ID INTEGER 0
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set_parameter_property PCORE_ID DEFAULT_VALUE 0
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set_parameter_property PCORE_ID DISPLAY_NAME PCORE_ID
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set_parameter_property PCORE_ID TYPE INTEGER
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set_parameter_property PCORE_ID UNITS None
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set_parameter_property PCORE_ID HDL_PARAMETER true
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add_parameter PCORE_DEVICE_TYPE INTEGER 0
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set_parameter_property PCORE_DEVICE_TYPE DEFAULT_VALUE 0
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set_parameter_property PCORE_DEVICE_TYPE DISPLAY_NAME PCORE_DEVICE_TYPE
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set_parameter_property PCORE_DEVICE_TYPE TYPE INTEGER
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set_parameter_property PCORE_DEVICE_TYPE UNITS None
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set_parameter_property PCORE_DEVICE_TYPE HDL_PARAMETER true
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add_parameter PCORE_4L_2L_N INTEGER 0
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set_parameter_property PCORE_4L_2L_N DEFAULT_VALUE 1
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set_parameter_property PCORE_4L_2L_N DISPLAY_NAME PCORE_4L_2L_N
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set_parameter_property PCORE_4L_2L_N TYPE INTEGER
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set_parameter_property PCORE_4L_2L_N UNITS None
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set_parameter_property PCORE_4L_2L_N HDL_PARAMETER true
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add_parameter PCORE_AXI_ID_WIDTH INTEGER 0
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set_parameter_property PCORE_AXI_ID_WIDTH DEFAULT_VALUE 3
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set_parameter_property PCORE_AXI_ID_WIDTH DISPLAY_NAME PCORE_AXI_ID_WIDTH
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set_parameter_property PCORE_AXI_ID_WIDTH TYPE INTEGER
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set_parameter_property PCORE_AXI_ID_WIDTH UNITS None
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set_parameter_property PCORE_AXI_ID_WIDTH HDL_PARAMETER true
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# axi4 slave
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add_interface s_axi_clock clock end
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add_interface_port s_axi_clock s_axi_aclk clk Input 1
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add_interface s_axi_reset reset end
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set_interface_property s_axi_reset associatedClock s_axi_clock
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add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1
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add_interface s_axi axi4 end
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set_interface_property s_axi associatedClock s_axi_clock
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set_interface_property s_axi associatedReset s_axi_reset
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add_interface_port s_axi s_axi_awvalid awvalid Input 1
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add_interface_port s_axi s_axi_awaddr awaddr Input 14
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add_interface_port s_axi s_axi_awready awready Output 1
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add_interface_port s_axi s_axi_wvalid wvalid Input 1
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add_interface_port s_axi s_axi_wdata wdata Input 32
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add_interface_port s_axi s_axi_wstrb wstrb Input 4
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add_interface_port s_axi s_axi_wready wready Output 1
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add_interface_port s_axi s_axi_bvalid bvalid Output 1
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add_interface_port s_axi s_axi_bresp bresp Output 2
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add_interface_port s_axi s_axi_bready bready Input 1
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add_interface_port s_axi s_axi_arvalid arvalid Input 1
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add_interface_port s_axi s_axi_araddr araddr Input 14
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add_interface_port s_axi s_axi_arready arready Output 1
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add_interface_port s_axi s_axi_rvalid rvalid Output 1
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add_interface_port s_axi s_axi_rresp rresp Output 2
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add_interface_port s_axi s_axi_rdata rdata Output 32
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add_interface_port s_axi s_axi_rready rready Input 1
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add_interface_port s_axi s_axi_awid awid Input PCORE_AXI_ID_WIDTH
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add_interface_port s_axi s_axi_awlen awlen Input 8
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add_interface_port s_axi s_axi_awsize awsize Input 3
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add_interface_port s_axi s_axi_awburst awburst Input 2
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add_interface_port s_axi s_axi_awlock awlock Input 1
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add_interface_port s_axi s_axi_awcache awcache Input 4
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add_interface_port s_axi s_axi_awprot awprot Input 3
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add_interface_port s_axi s_axi_wlast wlast Input 1
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add_interface_port s_axi s_axi_bid bid Output PCORE_AXI_ID_WIDTH
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add_interface_port s_axi s_axi_arid arid Input PCORE_AXI_ID_WIDTH
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add_interface_port s_axi s_axi_arlen arlen Input 8
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add_interface_port s_axi s_axi_arsize arsize Input 3
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add_interface_port s_axi s_axi_arburst arburst Input 2
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add_interface_port s_axi s_axi_arlock arlock Input 1
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add_interface_port s_axi s_axi_arcache arcache Input 4
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add_interface_port s_axi s_axi_arprot arprot Input 3
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add_interface_port s_axi s_axi_rid rid Output PCORE_AXI_ID_WIDTH
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add_interface_port s_axi s_axi_rlast rlast Output 1
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# transceiver interface
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add_interface xcvr_clk clock end
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add_interface_port xcvr_clk rx_clk clk Input 1
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add_interface xcvr_data conduit end
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set_interface_property xcvr_data associatedClock xcvr_clk
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add_interface_port xcvr_data rx_data data Input 64*PCORE_4L_2L_N+64
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# dma interface
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add_interface adc_clock clock start
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add_interface_port adc_clock adc_clk clk Output 1
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add_interface adc_dma_if conduit end
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set_interface_property adc_dma_if associatedClock adc_clock
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add_interface_port adc_dma_if adc_valid valid Output 7
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add_interface_port adc_dma_if adc_enable enable Output 7
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add_interface_port adc_dma_if adc_data data Output 128
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add_interface_port adc_dma_if adc_dovf dovf Input 1
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add_interface_port adc_dma_if adc_dunf dunf Input 1
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