Lars-Peter Clausen de4fe30238 library: Match s_axi_{awaddr,araddr} signal width to peripheral memory map size ... The external s_axi_{awaddr,araddr} signals that are connect to the core have their width set according to the specified size of the register map. If the s_axi_{awaddr,araddr} signal of the core is wider (as it currently is for many cores) the MSBs of those signals are left unconnected, which generates a warning. To avoid this make sure that the signal width matches the declared register map size. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>		2017-08-01 15:21:25 +02:00
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bd	axi_dmac: post_propagate(): Handle mappings with multiple address segments	2017-04-19 13:47:02 +02:00
2d_transfer.v	axi_dmac: Update to verilog-2001 coding style	2017-07-15 09:25:14 +01:00
Makefile	Create CDC helper library	2017-05-23 11:16:07 +02:00
address_generator.v	axi_dmac: Update to verilog-2001 coding style	2017-07-15 09:25:14 +01:00
axi_dmac.v	axi_dmac: Update to verilog-2001 coding style	2017-07-15 09:25:14 +01:00
axi_dmac_constr.sdc	axi_dmac: Removed unneded constraints, as FMCJESDADC1 doesn't work correctly with them	2015-07-23 17:01:02 +03:00
axi_dmac_constr.ttcl	axi_dmac: Make debug register optional	2017-04-18 12:17:39 +02:00
axi_dmac_hw.tcl	library: Match s_axi_{awaddr,araddr} signal width to peripheral memory map size	2017-08-01 15:21:25 +02:00
axi_dmac_ip.tcl	Create CDC helper library	2017-05-23 11:16:07 +02:00
axi_register_slice.v	axi_dmac: Update to verilog-2001 coding style	2017-07-15 09:25:14 +01:00
data_mover.v	axi_dmac: Update to verilog-2001 coding style	2017-07-15 09:25:14 +01:00
dest_axi_mm.v	axi_dmac: Update to verilog-2001 coding style	2017-07-15 09:25:14 +01:00
dest_axi_stream.v	axi_dmac: Update to verilog-2001 coding style	2017-07-15 09:25:14 +01:00
dest_fifo_inf.v	axi_dmac: Update to verilog-2001 coding style	2017-07-15 09:25:14 +01:00
inc_id.h	axi_dmac: Parameter changes	2015-08-20 16:06:26 +03:00
request_arb.v	axi_dmac: request_arb: Add missing req_gen_{valid,ready} signal declaration	2017-07-17 17:13:02 +02:00
request_generator.v	axi_dmac: Update to verilog-2001 coding style	2017-07-15 09:25:14 +01:00
resp.h	Added axi_dmac, axi_fifo and misc files in library	2014-03-06 18:16:02 +02:00
response_generator.v	axi_dmac: Update to verilog-2001 coding style	2017-07-15 09:25:14 +01:00
response_handler.v	axi_dmac: Update to verilog-2001 coding style	2017-07-15 09:25:14 +01:00
splitter.v	axi_dmac: Update to verilog-2001 coding style	2017-07-15 09:25:14 +01:00
src_axi_mm.v	axi_dmac: Update to verilog-2001 coding style	2017-07-15 09:25:14 +01:00
src_axi_stream.v	axi_dmac: Update to verilog-2001 coding style	2017-07-15 09:25:14 +01:00
src_fifo_inf.v	axi_dmac: Update to verilog-2001 coding style	2017-07-15 09:25:14 +01:00