112 lines
3.8 KiB
Verilog
112 lines
3.8 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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// fmc fpga interface
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eth_rx_clk,
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eth_rx_cntrl,
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eth_rx_data,
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eth_tx_clk_out,
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eth_tx_cntrl,
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eth_tx_data,
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eth_mdc,
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eth_mdio_i,
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eth_mdio_o,
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eth_mdio_t,
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// phy interface
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phy_resetn,
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phy_rx_clk,
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phy_rx_cntrl,
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phy_rx_data,
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phy_tx_clk_out,
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phy_tx_cntrl,
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phy_tx_data,
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phy_mdc,
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phy_mdio);
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// fmc fpga interface
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output eth_rx_clk;
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output eth_rx_cntrl;
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output [ 3:0] eth_rx_data;
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input eth_tx_clk_out;
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input eth_tx_cntrl;
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input [ 3:0] eth_tx_data;
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input eth_mdc;
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output eth_mdio_i;
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input eth_mdio_o;
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input eth_mdio_t;
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// phy interface
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output phy_resetn;
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input phy_rx_clk;
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input phy_rx_cntrl;
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input [ 3:0] phy_rx_data;
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output phy_tx_clk_out;
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output phy_tx_cntrl;
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output [ 3:0] phy_tx_data;
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output phy_mdc;
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inout phy_mdio;
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// simple pass through
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assign eth_rx_clk = phy_rx_clk;
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assign eth_rx_cntrl = phy_rx_cntrl;
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assign eth_rx_data = phy_rx_data;
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assign phy_tx_clk_out = eth_tx_clk_out;
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assign phy_tx_cntrl = eth_tx_cntrl;
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assign phy_tx_data = eth_tx_data;
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assign phy_mdc = eth_mdc;
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assign phy_mdio = (eth_mdio_t == 1'b0) ? eth_mdio_o : 1'bz;
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assign eth_mdio_i = phy_mdio;
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assign phy_resetn = 1'b1;
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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