782 lines
28 KiB
Verilog
782 lines
28 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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// board interface
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sys_rst,
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sys_clk_p,
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sys_clk_n,
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ddr3_a13,
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ddr3_we_n,
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ddr3_ras_n,
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ddr3_odt,
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ddr3_dqs_n,
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ddr3_dqs,
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ddr3_dq,
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ddr3_dm,
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ddr3_rst,
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ddr3_cs_n,
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ddr3_clk_n,
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ddr3_clk,
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ddr3_cke,
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ddr3_cas_n,
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ddr3_ba,
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ddr3_addr,
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uart_tx,
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uart_rx,
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phy_rstn,
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phy_mdc,
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phy_mdio,
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phy_crs,
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phy_col,
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phy_tx_clk,
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phy_tx_en,
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phy_tx_d,
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phy_rx_clk,
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phy_rx_dv,
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phy_rx_d,
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phy_rx_er,
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iic_scl,
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iic_sda,
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lcd,
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sw,
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led,
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// ad9361 interface
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rx_clk_in_p,
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rx_clk_in_n,
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rx_frame_in_p,
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rx_frame_in_n,
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rx_data_in_p,
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rx_data_in_n,
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tx_clk_out_p,
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tx_clk_out_n,
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tx_frame_out_p,
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tx_frame_out_n,
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tx_data_out_p,
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tx_data_out_n,
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gpio_txnrx,
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gpio_enable,
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gpio_resetb,
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gpio_sync,
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gpio_en_agc,
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gpio_ctl,
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gpio_status,
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spi_csn,
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spi_clk,
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spi_mosi,
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spi_miso);
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// board interface
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input sys_rst;
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input sys_clk_p;
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input sys_clk_n;
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output ddr3_a13;
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output ddr3_we_n;
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output ddr3_ras_n;
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output ddr3_odt;
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inout [ 7:0] ddr3_dqs_n;
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inout [ 7:0] ddr3_dqs;
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inout [ 63:0] ddr3_dq;
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output [ 7:0] ddr3_dm;
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output ddr3_rst;
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output ddr3_cs_n;
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output ddr3_clk_n;
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output ddr3_clk;
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output ddr3_cke;
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output ddr3_cas_n;
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output [ 2:0] ddr3_ba;
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output [ 12:0] ddr3_addr;
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output uart_tx;
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input uart_rx;
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output phy_rstn;
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output phy_mdc;
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inout phy_mdio;
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input phy_crs;
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input phy_col;
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input phy_tx_clk;
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output phy_tx_en;
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output [ 3:0] phy_tx_d;
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input phy_rx_clk;
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input phy_rx_dv;
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input [ 3:0] phy_rx_d;
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input phy_rx_er;
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inout iic_scl;
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inout iic_sda;
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inout [ 6:0] lcd;
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inout [ 12:0] sw;
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inout [ 12:0] led;
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// ad9361 interface
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input rx_clk_in_p;
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input rx_clk_in_n;
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input rx_frame_in_p;
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input rx_frame_in_n;
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input [ 5:0] rx_data_in_p;
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input [ 5:0] rx_data_in_n;
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output tx_clk_out_p;
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output tx_clk_out_n;
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output tx_frame_out_p;
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output tx_frame_out_n;
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output [ 5:0] tx_data_out_p;
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output [ 5:0] tx_data_out_n;
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inout gpio_txnrx;
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inout gpio_enable;
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inout gpio_resetb;
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inout gpio_sync;
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inout gpio_en_agc;
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inout [ 3:0] gpio_ctl;
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inout [ 7:0] gpio_status;
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output spi_csn;
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output spi_clk;
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output spi_mosi;
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input spi_miso;
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// internal signals
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wire [ 31:0] axi_gpio_fmc_i0;
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wire [ 31:0] axi_gpio_fmc_o0;
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wire [ 31:0] axi_gpio_fmc_t0;
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wire [ 31:0] axi_gpio_fmc_i1;
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wire [ 31:0] axi_gpio_fmc_o1;
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wire [ 31:0] axi_gpio_fmc_t1;
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wire axi_spi_fmc_sel;
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wire [ 7:0] axi_spi_fmc_csn_i;
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wire [ 7:0] axi_spi_fmc_csn_o;
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wire axi_spi_fmc_csn_t;
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wire axi_spi_fmc_clk_i;
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wire axi_spi_fmc_clk_o;
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wire axi_spi_fmc_clk_t;
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wire axi_spi_fmc_mosi_i;
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wire axi_spi_fmc_mosi_o;
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wire axi_spi_fmc_mosi_t;
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wire axi_spi_fmc_miso_i;
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wire axi_spi_fmc_miso_o;
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wire axi_spi_fmc_miso_t;
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wire axi_dma_tx_axil_aclk;
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wire axi_dma_tx_axil_aresetn;
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wire axi_dma_tx_axil_awvalid;
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wire [ 31:0] axi_dma_tx_axil_awaddr;
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wire axi_dma_tx_axil_awready;
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wire axi_dma_tx_axil_wvalid;
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wire [ 31:0] axi_dma_tx_axil_wdata;
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wire [ 3:0] axi_dma_tx_axil_wstrb;
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wire axi_dma_tx_axil_wready;
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wire axi_dma_tx_axil_bvalid;
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wire [ 1:0] axi_dma_tx_axil_bresp;
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wire axi_dma_tx_axil_bready;
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wire axi_dma_tx_axil_arvalid;
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wire [ 31:0] axi_dma_tx_axil_araddr;
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wire axi_dma_tx_axil_arready;
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wire axi_dma_tx_axil_rvalid;
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wire [ 31:0] axi_dma_tx_axil_rdata;
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wire [ 1:0] axi_dma_tx_axil_rresp;
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wire axi_dma_tx_axil_rready;
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wire axi_dma_tx_axim_s_aclk;
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wire axi_dma_tx_axim_s_aresetn;
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wire [ 31:0] axi_dma_tx_axim_s_araddr;
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wire [ 7:0] axi_dma_tx_axim_s_arlen;
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wire [ 2:0] axi_dma_tx_axim_s_arsize;
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wire [ 1:0] axi_dma_tx_axim_s_arburst;
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wire [ 2:0] axi_dma_tx_axim_s_arprot;
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wire [ 3:0] axi_dma_tx_axim_s_arcache;
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wire axi_dma_tx_axim_s_arready;
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wire axi_dma_tx_axim_s_arvalid;
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wire [ 1:0] axi_dma_tx_axim_s_rresp;
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wire [ 63:0] axi_dma_tx_axim_s_rdata;
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wire axi_dma_tx_axim_s_rready;
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wire axi_dma_tx_axim_s_rvalid;
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wire axi_dma_tx_axim_irq;
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wire axi_dma_rx_axil_aclk;
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wire axi_dma_rx_axil_aresetn;
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wire axi_dma_rx_axil_awvalid;
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wire [ 31:0] axi_dma_rx_axil_awaddr;
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wire axi_dma_rx_axil_awready;
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wire axi_dma_rx_axil_wvalid;
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wire [ 31:0] axi_dma_rx_axil_wdata;
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wire [ 3:0] axi_dma_rx_axil_wstrb;
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wire axi_dma_rx_axil_wready;
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wire axi_dma_rx_axil_bvalid;
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wire [ 1:0] axi_dma_rx_axil_bresp;
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wire axi_dma_rx_axil_bready;
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wire axi_dma_rx_axil_arvalid;
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wire [ 31:0] axi_dma_rx_axil_araddr;
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wire axi_dma_rx_axil_arready;
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wire axi_dma_rx_axil_rvalid;
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wire [ 31:0] axi_dma_rx_axil_rdata;
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wire [ 1:0] axi_dma_rx_axil_rresp;
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wire axi_dma_rx_axil_rready;
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wire axi_dma_rx_axim_d_aclk;
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wire axi_dma_rx_axim_d_aresetn;
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wire [ 31:0] axi_dma_rx_axim_d_awaddr;
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wire [ 7:0] axi_dma_rx_axim_d_awlen;
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wire [ 2:0] axi_dma_rx_axim_d_awsize;
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wire [ 1:0] axi_dma_rx_axim_d_awburst;
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wire [ 2:0] axi_dma_rx_axim_d_awprot;
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wire [ 3:0] axi_dma_rx_axim_d_awcache;
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wire axi_dma_rx_axim_d_awvalid;
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wire axi_dma_rx_axim_d_awready;
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wire [ 63:0] axi_dma_rx_axim_d_wdata;
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wire [ 7:0] axi_dma_rx_axim_d_wstrb;
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wire axi_dma_rx_axim_d_wready;
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wire axi_dma_rx_axim_d_wvalid;
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wire axi_dma_rx_axim_d_wlast;
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wire axi_dma_rx_axim_d_bready;
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wire [ 1:0] axi_dma_rx_axim_d_bresp;
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wire axi_dma_rx_axim_d_bvalid;
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wire axi_dma_rx_axim_irq;
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wire axi_dev_tx_axil_aclk;
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wire axi_dev_tx_axil_aresetn;
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wire axi_dev_tx_axil_awvalid;
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wire [ 31:0] axi_dev_tx_axil_awaddr;
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wire axi_dev_tx_axil_awready;
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wire axi_dev_tx_axil_wvalid;
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wire [ 31:0] axi_dev_tx_axil_wdata;
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wire [ 3:0] axi_dev_tx_axil_wstrb;
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wire axi_dev_tx_axil_wready;
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wire axi_dev_tx_axil_bvalid;
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wire [ 1:0] axi_dev_tx_axil_bresp;
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wire axi_dev_tx_axil_bready;
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wire axi_dev_tx_axil_arvalid;
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wire [ 31:0] axi_dev_tx_axil_araddr;
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wire axi_dev_tx_axil_arready;
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wire axi_dev_tx_axil_rvalid;
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wire [ 31:0] axi_dev_tx_axil_rdata;
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wire [ 1:0] axi_dev_tx_axil_rresp;
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wire axi_dev_tx_axil_rready;
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wire axi_dev_rx_axil_aclk;
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wire axi_dev_rx_axil_aresetn;
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wire axi_dev_rx_axil_awvalid;
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wire [ 31:0] axi_dev_rx_axil_awaddr;
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wire axi_dev_rx_axil_awready;
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wire axi_dev_rx_axil_wvalid;
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wire [ 31:0] axi_dev_rx_axil_wdata;
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wire [ 3:0] axi_dev_rx_axil_wstrb;
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wire axi_dev_rx_axil_wready;
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wire axi_dev_rx_axil_bvalid;
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wire [ 1:0] axi_dev_rx_axil_bresp;
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wire axi_dev_rx_axil_bready;
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wire axi_dev_rx_axil_arvalid;
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wire [ 31:0] axi_dev_rx_axil_araddr;
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wire axi_dev_rx_axil_arready;
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wire axi_dev_rx_axil_rvalid;
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wire [ 31:0] axi_dev_rx_axil_rdata;
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wire [ 1:0] axi_dev_rx_axil_rresp;
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wire axi_dev_rx_axil_rready;
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wire sys_200m_clk;
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wire clk;
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wire adc_dwr;
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wire [ 63:0] adc_ddata;
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wire adc_dsync;
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wire adc_dovf;
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wire dac_drd;
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wire [ 63:0] dac_ddata;
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wire dac_dunf;
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// gpio interface
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IOBUF i_iobuf_gpio_txnrx (
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.I (axi_gpio_fmc_o0[16]),
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.O (axi_gpio_fmc_i0[16]),
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.T (axi_gpio_fmc_t0[16]),
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.IO (gpio_txnrx));
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IOBUF i_iobuf_gpio_enable (
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.I (axi_gpio_fmc_o0[15]),
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.O (axi_gpio_fmc_i0[15]),
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.T (axi_gpio_fmc_t0[15]),
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.IO (gpio_enable));
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IOBUF i_iobuf_gpio_resetb (
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.I (axi_gpio_fmc_o0[14]),
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.O (axi_gpio_fmc_i0[14]),
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.T (axi_gpio_fmc_t0[14]),
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.IO (gpio_resetb));
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IOBUF i_iobuf_gpio_sync (
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.I (axi_gpio_fmc_o0[13]),
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.O (axi_gpio_fmc_i0[13]),
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.T (axi_gpio_fmc_t0[13]),
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.IO (gpio_sync));
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IOBUF i_iobuf_gpio_en_agc (
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.I (axi_gpio_fmc_o0[12]),
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.O (axi_gpio_fmc_i0[12]),
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.T (axi_gpio_fmc_t0[12]),
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.IO (gpio_en_agc));
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genvar n;
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generate
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for (n = 0; n <= 3; n = n + 1) begin: g_iobuf_gpio_ctl
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IOBUF i_iobuf_gpio_ctl (
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.I (axi_gpio_fmc_o0[8+n]),
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.O (axi_gpio_fmc_i0[8+n]),
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.T (axi_gpio_fmc_t0[8+n]),
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.IO (gpio_ctl[n]));
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end
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for (n = 0; n <= 7; n = n + 1) begin: g_iobuf_gpio_status
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IOBUF i_iobuf_gpio_status (
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.I (axi_gpio_fmc_o0[0+n]),
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.O (axi_gpio_fmc_i0[0+n]),
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.T (axi_gpio_fmc_t0[0+n]),
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.IO (gpio_status[n]));
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end
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endgenerate
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// spi interface
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assign spi_csn = axi_spi_fmc_csn_o[0];
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assign spi_clk = axi_spi_fmc_clk_o;
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assign spi_mosi = axi_spi_fmc_mosi_o;
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assign axi_spi_fmc_miso_i = spi_miso;
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// instantiations
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axi_ad9361 #(
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.PCORE_BUFTYPE (1),
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.C_BASEADDR (32'h00000000),
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.C_HIGHADDR (32'hffffffff))
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i_axi_ad9361 (
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.rx_clk_in_p (rx_clk_in_p),
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.rx_clk_in_n (rx_clk_in_n),
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.rx_frame_in_p (rx_frame_in_p),
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.rx_frame_in_n (rx_frame_in_n),
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.rx_data_in_p (rx_data_in_p),
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.rx_data_in_n (rx_data_in_n),
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.adc_start_in (1'd0),
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.adc_start_out (),
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.tx_clk_out_p (tx_clk_out_p),
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.tx_clk_out_n (tx_clk_out_n),
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.tx_frame_out_p (tx_frame_out_p),
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.tx_frame_out_n (tx_frame_out_n),
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.tx_data_out_p (tx_data_out_p),
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.tx_data_out_n (tx_data_out_n),
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.dac_enable_in (1'd0),
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.dac_enable_out (),
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.delay_clk (sys_200m_clk),
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.clk (clk),
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.adc_dwr (adc_dwr),
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.adc_ddata (adc_ddata),
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.adc_dsync (adc_dsync),
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.adc_dovf (adc_dovf),
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.adc_dunf (1'd0),
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.dac_drd (dac_drd),
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.dac_ddata (dac_ddata),
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.dac_dovf (1'd0),
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.dac_dunf (dac_dunf),
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.s_axi_aclk (axi_dev_tx_axil_aclk),
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.s_axi_aresetn (axi_dev_tx_axil_aresetn),
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.s_axi_awvalid (axi_dev_tx_axil_awvalid),
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.s_axi_awaddr (axi_dev_tx_axil_awaddr),
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.s_axi_awready (axi_dev_tx_axil_awready),
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.s_axi_wvalid (axi_dev_tx_axil_wvalid),
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.s_axi_wdata (axi_dev_tx_axil_wdata),
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.s_axi_wstrb (axi_dev_tx_axil_wstrb),
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.s_axi_wready (axi_dev_tx_axil_wready),
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.s_axi_bvalid (axi_dev_tx_axil_bvalid),
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.s_axi_bresp (axi_dev_tx_axil_bresp),
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.s_axi_bready (axi_dev_tx_axil_bready),
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.s_axi_arvalid (axi_dev_tx_axil_arvalid),
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.s_axi_araddr (axi_dev_tx_axil_araddr),
|
|
.s_axi_arready (axi_dev_tx_axil_arready),
|
|
.s_axi_rvalid (axi_dev_tx_axil_rvalid),
|
|
.s_axi_rdata (axi_dev_tx_axil_rdata),
|
|
.s_axi_rresp (axi_dev_tx_axil_rresp),
|
|
.s_axi_rready (axi_dev_tx_axil_rready),
|
|
.adc_mon_valid (),
|
|
.adc_mon_data ());
|
|
|
|
axi_dmac #(
|
|
.C_BASEADDR (32'h00000000),
|
|
.C_HIGHADDR (32'hffffffff),
|
|
.C_DMA_TYPE_SRC (0),
|
|
.C_DMA_TYPE_DEST (2),
|
|
.C_CYCLIC (1),
|
|
.C_SYNC_TRANSFER_START (0),
|
|
.C_AXI_SLICE_SRC (0),
|
|
.C_AXI_SLICE_DEST (1),
|
|
.C_CLKS_ASYNC_DEST_REQ (1),
|
|
.C_CLKS_ASYNC_SRC_DEST (1),
|
|
.C_CLKS_ASYNC_REQ_SRC (1),
|
|
.C_2D_TRANSFER (0))
|
|
i_axi_dmac_tx (
|
|
.s_axi_aclk (axi_dma_tx_axil_aclk),
|
|
.s_axi_aresetn (axi_dma_tx_axil_aresetn),
|
|
.s_axi_awvalid (axi_dma_tx_axil_awvalid),
|
|
.s_axi_awaddr (axi_dma_tx_axil_awaddr),
|
|
.s_axi_awready (axi_dma_tx_axil_awready),
|
|
.s_axi_wvalid (axi_dma_tx_axil_wvalid),
|
|
.s_axi_wdata (axi_dma_tx_axil_wdata),
|
|
.s_axi_wstrb (axi_dma_tx_axil_wstrb),
|
|
.s_axi_wready (axi_dma_tx_axil_wready),
|
|
.s_axi_bvalid (axi_dma_tx_axil_bvalid),
|
|
.s_axi_bresp (axi_dma_tx_axil_bresp),
|
|
.s_axi_bready (axi_dma_tx_axil_bready),
|
|
.s_axi_arvalid (axi_dma_tx_axil_arvalid),
|
|
.s_axi_araddr (axi_dma_tx_axil_araddr),
|
|
.s_axi_arready (axi_dma_tx_axil_arready),
|
|
.s_axi_rvalid (axi_dma_tx_axil_rvalid),
|
|
.s_axi_rready (axi_dma_tx_axil_rready),
|
|
.s_axi_rresp (axi_dma_tx_axil_rresp),
|
|
.s_axi_rdata (axi_dma_tx_axil_rdata),
|
|
.irq (axi_dma_tx_axim_irq),
|
|
.m_dest_axi_aclk (),
|
|
.m_dest_axi_aresetn (),
|
|
.m_src_axi_aclk (axi_dma_tx_axim_s_aclk),
|
|
.m_src_axi_aresetn (axi_dma_tx_axim_s_aresetn),
|
|
.m_dest_axi_awaddr (),
|
|
.m_dest_axi_awlen (),
|
|
.m_dest_axi_awsize (),
|
|
.m_dest_axi_awburst (),
|
|
.m_dest_axi_awprot (),
|
|
.m_dest_axi_awcache (),
|
|
.m_dest_axi_awvalid (),
|
|
.m_dest_axi_awready (),
|
|
.m_dest_axi_wdata (),
|
|
.m_dest_axi_wstrb (),
|
|
.m_dest_axi_wready (),
|
|
.m_dest_axi_wvalid (),
|
|
.m_dest_axi_wlast (),
|
|
.m_dest_axi_bvalid (),
|
|
.m_dest_axi_bresp (),
|
|
.m_dest_axi_bready (),
|
|
.m_src_axi_arready (axi_dma_tx_axim_s_arready),
|
|
.m_src_axi_arvalid (axi_dma_tx_axim_s_arvalid),
|
|
.m_src_axi_araddr (axi_dma_tx_axim_s_araddr),
|
|
.m_src_axi_arlen (axi_dma_tx_axim_s_arlen),
|
|
.m_src_axi_arsize (axi_dma_tx_axim_s_arsize),
|
|
.m_src_axi_arburst (axi_dma_tx_axim_s_arburst),
|
|
.m_src_axi_arprot (axi_dma_tx_axim_s_arprot),
|
|
.m_src_axi_arcache (axi_dma_tx_axim_s_arcache),
|
|
.m_src_axi_rdata (axi_dma_tx_axim_s_rdata),
|
|
.m_src_axi_rready (axi_dma_tx_axim_s_rready),
|
|
.m_src_axi_rvalid (axi_dma_tx_axim_s_rvalid),
|
|
.m_src_axi_rresp (axi_dma_tx_axim_s_rresp),
|
|
.s_axis_aclk (),
|
|
.s_axis_ready (),
|
|
.s_axis_valid (),
|
|
.s_axis_data (),
|
|
.s_axis_user (),
|
|
.m_axis_aclk (),
|
|
.m_axis_ready (),
|
|
.m_axis_valid (),
|
|
.m_axis_data (),
|
|
.fifo_wr_clk (),
|
|
.fifo_wr_en (),
|
|
.fifo_wr_din (),
|
|
.fifo_wr_overflow (),
|
|
.fifo_wr_sync (),
|
|
.fifo_rd_clk (clk),
|
|
.fifo_rd_en (dac_drd),
|
|
.fifo_rd_valid (),
|
|
.fifo_rd_dout (dac_ddata),
|
|
.fifo_rd_underflow (dac_dunf));
|
|
|
|
axi_dmac #(
|
|
.C_BASEADDR (32'h00000000),
|
|
.C_HIGHADDR (32'hffffffff),
|
|
.C_DMA_TYPE_SRC (2),
|
|
.C_DMA_TYPE_DEST (0),
|
|
.C_CYCLIC (0),
|
|
.C_SYNC_TRANSFER_START (1),
|
|
.C_AXI_SLICE_SRC (0),
|
|
.C_AXI_SLICE_DEST (0),
|
|
.C_CLKS_ASYNC_DEST_REQ (1),
|
|
.C_CLKS_ASYNC_SRC_DEST (1),
|
|
.C_CLKS_ASYNC_REQ_SRC (1),
|
|
.C_2D_TRANSFER (0))
|
|
i_axi_dmac_rx (
|
|
.s_axi_aclk (axi_dma_rx_axil_aclk),
|
|
.s_axi_aresetn (axi_dma_rx_axil_aresetn),
|
|
.s_axi_awvalid (axi_dma_rx_axil_awvalid),
|
|
.s_axi_awaddr (axi_dma_rx_axil_awaddr),
|
|
.s_axi_awready (axi_dma_rx_axil_awready),
|
|
.s_axi_wvalid (axi_dma_rx_axil_wvalid),
|
|
.s_axi_wdata (axi_dma_rx_axil_wdata),
|
|
.s_axi_wstrb (axi_dma_rx_axil_wstrb),
|
|
.s_axi_wready (axi_dma_rx_axil_wready),
|
|
.s_axi_bvalid (axi_dma_rx_axil_bvalid),
|
|
.s_axi_bresp (axi_dma_rx_axil_bresp),
|
|
.s_axi_bready (axi_dma_rx_axil_bready),
|
|
.s_axi_arvalid (axi_dma_rx_axil_arvalid),
|
|
.s_axi_araddr (axi_dma_rx_axil_araddr),
|
|
.s_axi_arready (axi_dma_rx_axil_arready),
|
|
.s_axi_rvalid (axi_dma_rx_axil_rvalid),
|
|
.s_axi_rready (axi_dma_rx_axil_rready),
|
|
.s_axi_rresp (axi_dma_rx_axil_rresp),
|
|
.s_axi_rdata (axi_dma_rx_axil_rdata),
|
|
.irq (axi_dma_rx_axim_irq),
|
|
.m_dest_axi_aclk (axi_dma_rx_axim_d_aclk),
|
|
.m_dest_axi_aresetn (axi_dma_rx_axim_d_aresetn),
|
|
.m_src_axi_aclk (),
|
|
.m_src_axi_aresetn (),
|
|
.m_dest_axi_awaddr (axi_dma_rx_axim_d_awaddr),
|
|
.m_dest_axi_awlen (axi_dma_rx_axim_d_awlen),
|
|
.m_dest_axi_awsize (axi_dma_rx_axim_d_awsize),
|
|
.m_dest_axi_awburst (axi_dma_rx_axim_d_awburst),
|
|
.m_dest_axi_awprot (axi_dma_rx_axim_d_awprot),
|
|
.m_dest_axi_awcache (axi_dma_rx_axim_d_awcache),
|
|
.m_dest_axi_awvalid (axi_dma_rx_axim_d_awvalid),
|
|
.m_dest_axi_awready (axi_dma_rx_axim_d_awready),
|
|
.m_dest_axi_wdata (axi_dma_rx_axim_d_wdata),
|
|
.m_dest_axi_wstrb (axi_dma_rx_axim_d_wstrb),
|
|
.m_dest_axi_wready (axi_dma_rx_axim_d_wready),
|
|
.m_dest_axi_wvalid (axi_dma_rx_axim_d_wvalid),
|
|
.m_dest_axi_wlast (axi_dma_rx_axim_d_wlast),
|
|
.m_dest_axi_bvalid (axi_dma_rx_axim_d_bvalid),
|
|
.m_dest_axi_bresp (axi_dma_rx_axim_d_bresp),
|
|
.m_dest_axi_bready (axi_dma_rx_axim_d_bready),
|
|
.m_src_axi_arready (),
|
|
.m_src_axi_arvalid (),
|
|
.m_src_axi_araddr (),
|
|
.m_src_axi_arlen (),
|
|
.m_src_axi_arsize (),
|
|
.m_src_axi_arburst (),
|
|
.m_src_axi_arprot (),
|
|
.m_src_axi_arcache (),
|
|
.m_src_axi_rdata (),
|
|
.m_src_axi_rready (),
|
|
.m_src_axi_rvalid (),
|
|
.m_src_axi_rresp (),
|
|
.s_axis_aclk (),
|
|
.s_axis_ready (),
|
|
.s_axis_valid (),
|
|
.s_axis_data (),
|
|
.s_axis_user (),
|
|
.m_axis_aclk (),
|
|
.m_axis_ready (),
|
|
.m_axis_valid (),
|
|
.m_axis_data (),
|
|
.fifo_wr_clk (clk),
|
|
.fifo_wr_en (adc_dwr),
|
|
.fifo_wr_din (adc_ddata),
|
|
.fifo_wr_overflow (adc_dovf),
|
|
.fifo_wr_sync (adc_dsync),
|
|
.fifo_rd_clk (),
|
|
.fifo_rd_en (),
|
|
.fifo_rd_valid (),
|
|
.fifo_rd_dout (),
|
|
.fifo_rd_underflow ());
|
|
|
|
system_stub i_system_stub (
|
|
.sys_rst (sys_rst),
|
|
.sys_clk_p (sys_clk_p),
|
|
.sys_clk_n (sys_clk_n),
|
|
.ddr3_a13 (ddr3_a13),
|
|
.ddr3_we_n (ddr3_we_n),
|
|
.ddr3_ras_n (ddr3_ras_n),
|
|
.ddr3_odt (ddr3_odt),
|
|
.ddr3_dqs_n (ddr3_dqs_n),
|
|
.ddr3_dqs (ddr3_dqs),
|
|
.ddr3_dq (ddr3_dq),
|
|
.ddr3_dm (ddr3_dm),
|
|
.ddr3_rst (ddr3_rst),
|
|
.ddr3_cs_n (ddr3_cs_n),
|
|
.ddr3_clk_n (ddr3_clk_n),
|
|
.ddr3_clk (ddr3_clk),
|
|
.ddr3_cke (ddr3_cke),
|
|
.ddr3_cas_n (ddr3_cas_n),
|
|
.ddr3_ba (ddr3_ba),
|
|
.ddr3_addr (ddr3_addr),
|
|
.uart_tx (uart_tx),
|
|
.uart_rx (uart_rx),
|
|
.phy_rstn (phy_rstn),
|
|
.phy_mdc (phy_mdc),
|
|
.phy_mdio (phy_mdio),
|
|
.phy_crs (phy_crs),
|
|
.phy_col (phy_col),
|
|
.phy_tx_clk (phy_tx_clk),
|
|
.phy_tx_en (phy_tx_en),
|
|
.phy_tx_d (phy_tx_d),
|
|
.phy_rx_clk (phy_rx_clk),
|
|
.phy_rx_dv (phy_rx_dv),
|
|
.phy_rx_d (phy_rx_d),
|
|
.phy_rx_er (phy_rx_er),
|
|
.iic_scl (iic_scl),
|
|
.iic_sda (iic_sda),
|
|
.lcd (lcd),
|
|
.sw (sw),
|
|
.led (led),
|
|
.axi_gpio_fmc_i0 (axi_gpio_fmc_i0),
|
|
.axi_gpio_fmc_o0 (axi_gpio_fmc_o0),
|
|
.axi_gpio_fmc_t0 (axi_gpio_fmc_t0),
|
|
.axi_gpio_fmc_i1 (axi_gpio_fmc_i1),
|
|
.axi_gpio_fmc_o1 (axi_gpio_fmc_o1),
|
|
.axi_gpio_fmc_t1 (axi_gpio_fmc_t1),
|
|
.axi_spi_fmc_sel (axi_spi_fmc_sel),
|
|
.axi_spi_fmc_csn_i (axi_spi_fmc_csn_i),
|
|
.axi_spi_fmc_csn_o (axi_spi_fmc_csn_o),
|
|
.axi_spi_fmc_csn_t (axi_spi_fmc_csn_t),
|
|
.axi_spi_fmc_clk_i (axi_spi_fmc_clk_i),
|
|
.axi_spi_fmc_clk_o (axi_spi_fmc_clk_o),
|
|
.axi_spi_fmc_clk_t (axi_spi_fmc_clk_t),
|
|
.axi_spi_fmc_mosi_i (axi_spi_fmc_mosi_i),
|
|
.axi_spi_fmc_mosi_o (axi_spi_fmc_mosi_o),
|
|
.axi_spi_fmc_mosi_t (axi_spi_fmc_mosi_t),
|
|
.axi_spi_fmc_miso_i (axi_spi_fmc_miso_i),
|
|
.axi_spi_fmc_miso_o (axi_spi_fmc_miso_o),
|
|
.axi_spi_fmc_miso_t (axi_spi_fmc_miso_t),
|
|
.axi_dma_tx_axil_aclk (axi_dma_tx_axil_aclk),
|
|
.axi_dma_tx_axil_aresetn (axi_dma_tx_axil_aresetn),
|
|
.axi_dma_tx_axil_awvalid (axi_dma_tx_axil_awvalid),
|
|
.axi_dma_tx_axil_awaddr (axi_dma_tx_axil_awaddr),
|
|
.axi_dma_tx_axil_awready (axi_dma_tx_axil_awready),
|
|
.axi_dma_tx_axil_wvalid (axi_dma_tx_axil_wvalid),
|
|
.axi_dma_tx_axil_wdata (axi_dma_tx_axil_wdata),
|
|
.axi_dma_tx_axil_wstrb (axi_dma_tx_axil_wstrb),
|
|
.axi_dma_tx_axil_wready (axi_dma_tx_axil_wready),
|
|
.axi_dma_tx_axil_bvalid (axi_dma_tx_axil_bvalid),
|
|
.axi_dma_tx_axil_bresp (axi_dma_tx_axil_bresp),
|
|
.axi_dma_tx_axil_bready (axi_dma_tx_axil_bready),
|
|
.axi_dma_tx_axil_arvalid (axi_dma_tx_axil_arvalid),
|
|
.axi_dma_tx_axil_araddr (axi_dma_tx_axil_araddr),
|
|
.axi_dma_tx_axil_arready (axi_dma_tx_axil_arready),
|
|
.axi_dma_tx_axil_rvalid (axi_dma_tx_axil_rvalid),
|
|
.axi_dma_tx_axil_rdata (axi_dma_tx_axil_rdata),
|
|
.axi_dma_tx_axil_rresp (axi_dma_tx_axil_rresp),
|
|
.axi_dma_tx_axil_rready (axi_dma_tx_axil_rready),
|
|
.axi_dma_tx_axim_s_aclk (axi_dma_tx_axim_s_aclk),
|
|
.axi_dma_tx_axim_s_aresetn (axi_dma_tx_axim_s_aresetn),
|
|
.axi_dma_tx_axim_s_araddr (axi_dma_tx_axim_s_araddr),
|
|
.axi_dma_tx_axim_s_arlen (axi_dma_tx_axim_s_arlen),
|
|
.axi_dma_tx_axim_s_arsize (axi_dma_tx_axim_s_arsize),
|
|
.axi_dma_tx_axim_s_arburst (axi_dma_tx_axim_s_arburst),
|
|
.axi_dma_tx_axim_s_arprot (axi_dma_tx_axim_s_arprot),
|
|
.axi_dma_tx_axim_s_arcache (axi_dma_tx_axim_s_arcache),
|
|
.axi_dma_tx_axim_s_arready (axi_dma_tx_axim_s_arready),
|
|
.axi_dma_tx_axim_s_arvalid (axi_dma_tx_axim_s_arvalid),
|
|
.axi_dma_tx_axim_s_rresp (axi_dma_tx_axim_s_rresp),
|
|
.axi_dma_tx_axim_s_rdata (axi_dma_tx_axim_s_rdata),
|
|
.axi_dma_tx_axim_s_rready (axi_dma_tx_axim_s_rready),
|
|
.axi_dma_tx_axim_s_rvalid (axi_dma_tx_axim_s_rvalid),
|
|
.axi_dma_tx_axim_irq (axi_dma_tx_axim_irq),
|
|
.axi_dma_rx_axil_aclk (axi_dma_rx_axil_aclk),
|
|
.axi_dma_rx_axil_aresetn (axi_dma_rx_axil_aresetn),
|
|
.axi_dma_rx_axil_awvalid (axi_dma_rx_axil_awvalid),
|
|
.axi_dma_rx_axil_awaddr (axi_dma_rx_axil_awaddr),
|
|
.axi_dma_rx_axil_awready (axi_dma_rx_axil_awready),
|
|
.axi_dma_rx_axil_wvalid (axi_dma_rx_axil_wvalid),
|
|
.axi_dma_rx_axil_wdata (axi_dma_rx_axil_wdata),
|
|
.axi_dma_rx_axil_wstrb (axi_dma_rx_axil_wstrb),
|
|
.axi_dma_rx_axil_wready (axi_dma_rx_axil_wready),
|
|
.axi_dma_rx_axil_bvalid (axi_dma_rx_axil_bvalid),
|
|
.axi_dma_rx_axil_bresp (axi_dma_rx_axil_bresp),
|
|
.axi_dma_rx_axil_bready (axi_dma_rx_axil_bready),
|
|
.axi_dma_rx_axil_arvalid (axi_dma_rx_axil_arvalid),
|
|
.axi_dma_rx_axil_araddr (axi_dma_rx_axil_araddr),
|
|
.axi_dma_rx_axil_arready (axi_dma_rx_axil_arready),
|
|
.axi_dma_rx_axil_rvalid (axi_dma_rx_axil_rvalid),
|
|
.axi_dma_rx_axil_rdata (axi_dma_rx_axil_rdata),
|
|
.axi_dma_rx_axil_rresp (axi_dma_rx_axil_rresp),
|
|
.axi_dma_rx_axil_rready (axi_dma_rx_axil_rready),
|
|
.axi_dma_rx_axim_d_aclk (axi_dma_rx_axim_d_aclk),
|
|
.axi_dma_rx_axim_d_aresetn (axi_dma_rx_axim_d_aresetn),
|
|
.axi_dma_rx_axim_d_awaddr (axi_dma_rx_axim_d_awaddr),
|
|
.axi_dma_rx_axim_d_awlen (axi_dma_rx_axim_d_awlen),
|
|
.axi_dma_rx_axim_d_awsize (axi_dma_rx_axim_d_awsize),
|
|
.axi_dma_rx_axim_d_awburst (axi_dma_rx_axim_d_awburst),
|
|
.axi_dma_rx_axim_d_awprot (axi_dma_rx_axim_d_awprot),
|
|
.axi_dma_rx_axim_d_awcache (axi_dma_rx_axim_d_awcache),
|
|
.axi_dma_rx_axim_d_awvalid (axi_dma_rx_axim_d_awvalid),
|
|
.axi_dma_rx_axim_d_awready (axi_dma_rx_axim_d_awready),
|
|
.axi_dma_rx_axim_d_wdata (axi_dma_rx_axim_d_wdata),
|
|
.axi_dma_rx_axim_d_wstrb (axi_dma_rx_axim_d_wstrb),
|
|
.axi_dma_rx_axim_d_wready (axi_dma_rx_axim_d_wready),
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.axi_dma_rx_axim_d_wvalid (axi_dma_rx_axim_d_wvalid),
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.axi_dma_rx_axim_d_wlast (axi_dma_rx_axim_d_wlast),
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.axi_dma_rx_axim_d_bready (axi_dma_rx_axim_d_bready),
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.axi_dma_rx_axim_d_bresp (axi_dma_rx_axim_d_bresp),
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.axi_dma_rx_axim_d_bvalid (axi_dma_rx_axim_d_bvalid),
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.axi_dma_rx_axim_irq (axi_dma_rx_axim_irq),
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|
.axi_dev_tx_axil_aclk (axi_dev_tx_axil_aclk),
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.axi_dev_tx_axil_aresetn (axi_dev_tx_axil_aresetn),
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.axi_dev_tx_axil_awvalid (axi_dev_tx_axil_awvalid),
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|
.axi_dev_tx_axil_awaddr (axi_dev_tx_axil_awaddr),
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|
.axi_dev_tx_axil_awready (axi_dev_tx_axil_awready),
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|
.axi_dev_tx_axil_wvalid (axi_dev_tx_axil_wvalid),
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|
.axi_dev_tx_axil_wdata (axi_dev_tx_axil_wdata),
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|
.axi_dev_tx_axil_wstrb (axi_dev_tx_axil_wstrb),
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|
.axi_dev_tx_axil_wready (axi_dev_tx_axil_wready),
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|
.axi_dev_tx_axil_bvalid (axi_dev_tx_axil_bvalid),
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|
.axi_dev_tx_axil_bresp (axi_dev_tx_axil_bresp),
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|
.axi_dev_tx_axil_bready (axi_dev_tx_axil_bready),
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|
.axi_dev_tx_axil_arvalid (axi_dev_tx_axil_arvalid),
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|
.axi_dev_tx_axil_araddr (axi_dev_tx_axil_araddr),
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|
.axi_dev_tx_axil_arready (axi_dev_tx_axil_arready),
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|
.axi_dev_tx_axil_rvalid (axi_dev_tx_axil_rvalid),
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|
.axi_dev_tx_axil_rdata (axi_dev_tx_axil_rdata),
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|
.axi_dev_tx_axil_rresp (axi_dev_tx_axil_rresp),
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|
.axi_dev_tx_axil_rready (axi_dev_tx_axil_rready),
|
|
.axi_dev_rx_axil_aclk (axi_dev_rx_axil_aclk),
|
|
.axi_dev_rx_axil_aresetn (axi_dev_rx_axil_aresetn),
|
|
.axi_dev_rx_axil_awvalid (axi_dev_rx_axil_awvalid),
|
|
.axi_dev_rx_axil_awaddr (axi_dev_rx_axil_awaddr),
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|
.axi_dev_rx_axil_awready (axi_dev_rx_axil_awready),
|
|
.axi_dev_rx_axil_wvalid (axi_dev_rx_axil_wvalid),
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|
.axi_dev_rx_axil_wdata (axi_dev_rx_axil_wdata),
|
|
.axi_dev_rx_axil_wstrb (axi_dev_rx_axil_wstrb),
|
|
.axi_dev_rx_axil_wready (axi_dev_rx_axil_wready),
|
|
.axi_dev_rx_axil_bvalid (axi_dev_rx_axil_bvalid),
|
|
.axi_dev_rx_axil_bresp (axi_dev_rx_axil_bresp),
|
|
.axi_dev_rx_axil_bready (axi_dev_rx_axil_bready),
|
|
.axi_dev_rx_axil_arvalid (axi_dev_rx_axil_arvalid),
|
|
.axi_dev_rx_axil_araddr (axi_dev_rx_axil_araddr),
|
|
.axi_dev_rx_axil_arready (axi_dev_rx_axil_arready),
|
|
.axi_dev_rx_axil_rvalid (axi_dev_rx_axil_rvalid),
|
|
.axi_dev_rx_axil_rdata (axi_dev_rx_axil_rdata),
|
|
.axi_dev_rx_axil_rresp (axi_dev_rx_axil_rresp),
|
|
.axi_dev_rx_axil_rready (axi_dev_rx_axil_rready),
|
|
.sys_200m_clk (sys_200m_clk));
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|
|
|
endmodule
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// ***************************************************************************
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// ***************************************************************************
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