154 lines
4.8 KiB
Verilog
154 lines
4.8 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2013(c) Analog Devices, Inc.
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// Author: Lars-Peter Clausen <lars@metafoo.de>
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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module dmac_dest_axi_stream (
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input s_axis_aclk,
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input s_axis_aresetn,
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input enable,
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output enabled,
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input sync_id,
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output sync_id_ret,
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output xfer_req,
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input [ID_WIDTH-1:0] request_id,
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output [ID_WIDTH-1:0] response_id,
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output [ID_WIDTH-1:0] data_id,
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input data_eot,
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input response_eot,
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input m_axis_ready,
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output m_axis_valid,
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output [S_AXIS_DATA_WIDTH-1:0] m_axis_data,
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output m_axis_last,
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output fifo_ready,
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input fifo_valid,
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input [S_AXIS_DATA_WIDTH-1:0] fifo_data,
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input req_valid,
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output req_ready,
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input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
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input req_xlast,
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output response_valid,
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input response_ready,
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output response_resp_eot,
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output [1:0] response_resp
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);
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parameter ID_WIDTH = 3;
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parameter S_AXIS_DATA_WIDTH = 64;
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parameter BEATS_PER_BURST_WIDTH = 4;
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reg req_xlast_d = 1'b0;
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assign sync_id_ret = sync_id;
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wire data_enabled;
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wire _fifo_ready;
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wire m_axis_last_s;
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// We are not allowed to just de-assert valid, but if the streaming target does
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// not accept any samples anymore we'd lock up the DMA core. So retain the last
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// beat when disabled until it is accepted. But if in the meantime the DMA core
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// is re-enabled and new data becomes available overwrite the old.
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always @(posedge s_axis_aclk) begin
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if(req_ready == 1'b1) begin
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req_xlast_d <= req_xlast;
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end
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end
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assign m_axis_last = (req_xlast_d == 1'b1) ? m_axis_last_s : 1'b0;
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dmac_data_mover # (
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.ID_WIDTH(ID_WIDTH),
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.DATA_WIDTH(S_AXIS_DATA_WIDTH),
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.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
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.DISABLE_WAIT_FOR_ID(0)
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) i_data_mover (
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.clk(s_axis_aclk),
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.resetn(s_axis_aresetn),
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.enable(enable),
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.enabled(data_enabled),
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.sync_id(sync_id),
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.xfer_req(xfer_req),
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.request_id(request_id),
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.response_id(data_id),
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.eot(data_eot),
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.req_valid(req_valid),
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.req_ready(req_ready),
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.req_last_burst_length(req_last_burst_length),
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.m_axi_ready(m_axis_ready),
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.m_axi_valid(m_axis_valid),
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.m_axi_data(m_axis_data),
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.m_axi_last(m_axis_last_s),
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.s_axi_ready(_fifo_ready),
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.s_axi_valid(fifo_valid),
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.s_axi_data(fifo_data)
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);
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dmac_response_generator # (
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.ID_WIDTH(ID_WIDTH)
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) i_response_generator (
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.clk(s_axis_aclk),
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.resetn(s_axis_aresetn),
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.enable(data_enabled),
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.enabled(enabled),
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.sync_id(sync_id),
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.request_id(data_id),
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.response_id(response_id),
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.eot(response_eot),
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.resp_valid(response_valid),
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.resp_ready(response_ready),
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.resp_eot(response_resp_eot),
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.resp_resp(response_resp)
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);
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assign fifo_ready = _fifo_ready | ~enabled;
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endmodule
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