322 lines
10 KiB
VHDL
322 lines
10 KiB
VHDL
------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Copyright 2011-2013(c) Analog Devices, Inc.
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--
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without modification,
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-- are permitted provided that the following conditions are met:
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-- - Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- - Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in
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-- the documentation and/or other materials provided with the
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-- distribution.
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-- - Neither the name of Analog Devices, Inc. nor the names of its
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-- contributors may be used to endorse or promote products derived
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-- from this software without specific prior written permission.
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-- - The use of this software may or may not infringe the patent rights
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-- of one or more patent holders. This license does not release you
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-- from the requirement that you obtain separate licenses from these
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-- patent holders to use this software.
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-- - Use of the software either in source or binary form, must be run
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-- on or directly connected to an Analog Devices Inc. component.
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--
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-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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-- PARTICULAR PURPOSE ARE DISCLAIMED.
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--
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-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- andrei.cozma@analog.com (c) Analog Devices Inc.
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library work;
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use work.tx_package.all;
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use work.axi_ctrlif;
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use work.axi_streaming_dma_tx_fifo;
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use work.pl330_dma_fifo;
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entity axi_spdif_tx is
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generic (
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S_AXI_DATA_WIDTH : integer := 32;
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S_AXI_ADDRESS_WIDTH : integer := 32;
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DEVICE_FAMILY : string := "virtex6";
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DMA_TYPE : integer := 0
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);
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port (
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--SPDIF ports
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spdif_data_clk : in std_logic;
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spdif_tx_o : out std_logic;
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--AXI Lite interface
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S_AXI_ACLK : in std_logic;
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S_AXI_ARESETN : in std_logic;
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S_AXI_AWADDR : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0);
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S_AXI_AWVALID : in std_logic;
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S_AXI_WDATA : in std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
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S_AXI_WSTRB : in std_logic_vector((S_AXI_DATA_WIDTH/8)-1 downto 0);
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S_AXI_WVALID : in std_logic;
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S_AXI_BREADY : in std_logic;
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S_AXI_ARADDR : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0);
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S_AXI_ARVALID : in std_logic;
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S_AXI_RREADY : in std_logic;
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S_AXI_ARREADY : out std_logic;
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S_AXI_RDATA : out std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
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S_AXI_RRESP : out std_logic_vector(1 downto 0);
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S_AXI_RVALID : out std_logic;
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S_AXI_WREADY : out std_logic;
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S_AXI_BRESP : out std_logic_vector(1 downto 0);
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S_AXI_BVALID : out std_logic;
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S_AXI_AWREADY : out std_logic;
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--AXI streaming interface
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S_AXIS_ACLK : in std_logic;
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S_AXIS_ARESETN : in std_logic;
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S_AXIS_TREADY : out std_logic;
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S_AXIS_TDATA : in std_logic_vector(31 downto 0);
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S_AXIS_TLAST : in std_logic;
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S_AXIS_TVALID : in std_logic;
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--PL330 DMA interface
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DMA_REQ_ACLK : in std_logic;
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DMA_REQ_RSTN : in std_logic;
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DMA_REQ_DAVALID : in std_logic;
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DMA_REQ_DATYPE : in std_logic_vector(1 downto 0);
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DMA_REQ_DAREADY : out std_logic;
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DMA_REQ_DRVALID : out std_logic;
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DMA_REQ_DRTYPE : out std_logic_vector(1 downto 0);
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DMA_REQ_DRLAST : out std_logic;
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DMA_REQ_DRREADY : in std_logic
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);
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end entity axi_spdif_tx;
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------------------------------------------------------------------------------
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-- Architecture section
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------------------------------------------------------------------------------
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architecture IMP of axi_spdif_tx is
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------------------------------------------
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-- SPDIF signals
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------------------------------------------
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signal config_reg : std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
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signal chstatus_reg : std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
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signal chstat_freq : std_logic_vector(1 downto 0);
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signal chstat_gstat, chstat_preem, chstat_copy, chstat_audio : std_logic;
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signal sample_data_ack : std_logic;
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signal sample_data: std_logic_vector(15 downto 0);
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signal conf_mode : std_logic_vector(3 downto 0);
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signal conf_ratio : std_logic_vector(7 downto 0);
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signal conf_tinten, conf_txdata, conf_txen : std_logic;
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signal channel : std_logic;
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signal enable : boolean;
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signal fifo_data_out : std_logic_vector(31 downto 0);
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signal fifo_data_ack : std_logic;
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signal fifo_reset : std_logic;
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signal tx_fifo_stb : std_logic;
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-- Register access
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signal wr_data : std_logic_vector(31 downto 0);
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signal rd_data : std_logic_vector(31 downto 0);
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signal wr_addr : integer range 0 to 3;
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signal rd_addr : integer range 0 to 3;
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signal wr_stb : std_logic;
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signal rd_ack : std_logic;
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begin
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fifo_reset <= not conf_txdata;
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enable <= conf_txdata = '1';
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fifo_data_ack <= channel and sample_data_ack;
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streaming_dma_gen: if DMA_TYPE = 0 generate
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fifo: entity axi_streaming_dma_tx_fifo
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generic map (
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RAM_ADDR_WIDTH => 3,
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FIFO_DWIDTH => 32
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)
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port map (
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clk => S_AXI_ACLK,
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resetn => S_AXI_ARESETN,
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fifo_reset => fifo_reset,
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enable => enable,
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S_AXIS_ACLK => S_AXIS_ACLK,
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S_AXIS_TREADY => S_AXIS_TREADY,
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S_AXIS_TDATA => S_AXIS_TDATA,
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S_AXIS_TVALID => S_AXIS_TLAST,
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S_AXIS_TLAST => S_AXIS_TVALID,
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out_ack => fifo_data_ack,
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out_data => fifo_data_out
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);
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end generate;
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no_streaming_dma_gen: if DMA_TYPE /= 0 generate
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S_AXIS_TREADY <= '0';
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end generate;
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pl330_dma_gen: if DMA_TYPE = 1 generate
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tx_fifo_stb <= '1' when wr_addr = 3 and wr_stb = '1' else '0';
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fifo: entity pl330_dma_fifo
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generic map(
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RAM_ADDR_WIDTH => 3,
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FIFO_DWIDTH => 32,
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FIFO_DIRECTION => 0
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)
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port map (
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clk => S_AXI_ACLK,
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resetn => S_AXI_ARESETN,
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fifo_reset => fifo_reset,
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enable => enable,
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in_data => wr_data,
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in_stb => tx_fifo_stb,
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out_ack => fifo_data_ack,
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out_data => fifo_data_out,
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dclk => DMA_REQ_ACLK,
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dresetn => DMA_REQ_RSTN,
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davalid => DMA_REQ_DAVALID,
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daready => DMA_REQ_DAREADY,
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datype => DMA_REQ_DATYPE,
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drvalid => DMA_REQ_DRVALID,
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drready => DMA_REQ_DRREADY,
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drtype => DMA_REQ_DRTYPE,
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drlast => DMA_REQ_DRLAST
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);
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end generate;
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no_pl330_dma_gen: if DMA_TYPE /= 1 generate
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DMA_REQ_DAREADY <= '0';
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DMA_REQ_DRVALID <= '0';
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DMA_REQ_DRTYPE <= (others => '0');
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DMA_REQ_DRLAST <= '0';
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end generate;
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sample_data_mux: process (fifo_data_out, channel) is
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begin
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if channel = '0' then
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sample_data <= fifo_data_out(15 downto 0);
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else
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sample_data <= fifo_data_out(31 downto 16);
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end if;
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end process;
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-- Configuration signals update
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conf_mode(3 downto 0) <= config_reg(23 downto 20);
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conf_ratio(7 downto 0) <= config_reg(15 downto 8);
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conf_tinten <= config_reg(2);
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conf_txdata <= config_reg(1);
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conf_txen <= config_reg(0);
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-- Channel status signals update
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chstat_freq(1 downto 0) <= chstatus_reg(7 downto 6);
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chstat_gstat <= chstatus_reg(3);
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chstat_preem <= chstatus_reg(2);
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chstat_copy <= chstatus_reg(1);
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chstat_audio <= chstatus_reg(0);
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-- Transmit encoder
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TENC: tx_encoder
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generic map (
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DATA_WIDTH => 16
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)
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port map (
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up_clk => S_AXI_ACLK,
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data_clk => spdif_data_clk, -- data clock
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resetn => S_AXI_ARESETN, -- resetn
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conf_mode => conf_mode, -- sample format
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conf_ratio => conf_ratio, -- clock divider
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conf_txdata => conf_txdata, -- sample data enable
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conf_txen => conf_txen, -- spdif signal enable
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chstat_freq => chstat_freq, -- sample freq.
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chstat_gstat => chstat_gstat, -- generation status
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chstat_preem => chstat_preem, -- preemphasis status
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chstat_copy => chstat_copy, -- copyright bit
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chstat_audio => chstat_audio, -- data format
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sample_data => sample_data, -- audio data
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sample_data_ack => sample_data_ack, -- sample buffer read
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channel => channel, -- which channel should be read
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spdif_tx_o => spdif_tx_o -- SPDIF output signal
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);
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ctrlif: entity axi_ctrlif
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generic map (
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C_S_AXI_ADDR_WIDTH => S_AXI_ADDRESS_WIDTH,
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C_S_AXI_DATA_WIDTH => S_AXI_DATA_WIDTH,
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C_NUM_REG => 4
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)
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port map(
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S_AXI_ACLK => S_AXI_ACLK,
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S_AXI_ARESETN => S_AXI_ARESETN,
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S_AXI_AWADDR => S_AXI_AWADDR,
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S_AXI_AWVALID => S_AXI_AWVALID,
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S_AXI_WDATA => S_AXI_WDATA,
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S_AXI_WSTRB => S_AXI_WSTRB,
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S_AXI_WVALID => S_AXI_WVALID,
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S_AXI_BREADY => S_AXI_BREADY,
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S_AXI_ARADDR => S_AXI_ARADDR,
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S_AXI_ARVALID => S_AXI_ARVALID,
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S_AXI_RREADY => S_AXI_RREADY,
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S_AXI_ARREADY => S_AXI_ARREADY,
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S_AXI_RDATA => S_AXI_RDATA,
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S_AXI_RRESP => S_AXI_RRESP,
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S_AXI_RVALID => S_AXI_RVALID,
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S_AXI_WREADY => S_AXI_WREADY,
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S_AXI_BRESP => S_AXI_BRESP,
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S_AXI_BVALID => S_AXI_BVALID,
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S_AXI_AWREADY => S_AXI_AWREADY,
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rd_addr => rd_addr,
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rd_data => rd_data,
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rd_ack => rd_ack,
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rd_stb => '1',
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wr_addr => wr_addr,
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wr_data => wr_data,
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wr_ack => '1',
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wr_stb => wr_stb
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);
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process (S_AXI_ACLK)
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begin
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if rising_edge(S_AXI_ACLK) then
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if S_AXI_ARESETN = '0' then
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config_reg <= (others => '0');
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chstatus_reg <= (others => '0');
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else
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if wr_stb = '1' then
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case wr_addr is
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when 0 => config_reg <= wr_data;
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when 1 => chstatus_reg <= wr_data;
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when others => null;
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end case;
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end if;
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end if;
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end if;
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end process;
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process (rd_addr, config_reg, chstatus_reg)
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begin
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case rd_addr is
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when 0 => rd_data <= config_reg;
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when 1 => rd_data <= chstatus_reg;
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when others => rd_data <= (others => '0');
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end case;
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end process;
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end IMP;
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