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Istvan Csomortani e0b7ef2f4f scripts: Update scripts for PR design flow 
+ Rewrite the pr_verify process, to improve verification time
 + Update the implementation flow: always the biggest logic will be implemented first, to achieve a better result
    therefore force the tool to optimize the first logic with 'ExploreSequentialArea'
 + Make utilization report just from the PR pblock, that's more relevant as the utilization report of the whole fabric
 		2014-10-30 18:51:13 +02:00
library axi_fifo2f: internal memory low overhead 2014-10-30 11:12:10 -04:00
projects scripts: Update scripts for PR design flow 2014-10-30 18:51:13 +02:00
.gitignore a5soc: increase pipeline for qsys 2014-05-04 10:38:53 -04:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
README.md Add a link to EngineerZone 2014-04-15 10:25:18 +03:00

README.md

hdl

Analog Devices HDL libraries and projects

First time users, it is highly recommended to go through our HDL user guide at the following url:

http://wiki.analog.com/resources/fpga/docs/hdl

For support please visit our FPGA Reference Designs Support Community on EngineerZone:

http://ez.analog.com/community/fpga