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Istvan Csomortani e1d8dd10a9 daq2: Initial check in of the VC707 based project 
NOTE: Can not communicate with the clock chip, rx/tx PLL not locking.
 		2015-01-28 16:24:06 +02:00
library axi_dmac: Fix constraint 2015-01-23 18:51:25 +02:00
projects daq2: Initial check in of the VC707 based project 2015-01-28 16:24:06 +02:00
.gitignore a5soc: increase pipeline for qsys 2014-05-04 10:38:53 -04:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
README.md README: Add tools version 2015-01-07 14:02:38 -05:00

README.md

hdl

Analog Devices HDL libraries and projects

Tools version:

  • Vivado 2014.2
  • Quartus 14.0

First time users, it is highly recommended to go through our HDL user guide at the following url:

http://wiki.analog.com/resources/fpga/docs/hdl

For support please visit our FPGA Reference Designs Support Community on EngineerZone:

http://ez.analog.com/community/fpga