424 lines
14 KiB
Verilog
424 lines
14 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9361_tx_channel (
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// dac interface
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dac_clk,
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dac_rst,
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dac_valid,
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dma_data,
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adc_data,
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dac_data,
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dac_data_out,
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dac_data_in,
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// processor interface
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dac_enable,
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dac_data_sync,
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dac_dds_format,
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// bus interface
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up_rstn,
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up_clk,
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up_wreq,
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up_waddr,
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up_wdata,
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up_wack,
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up_rreq,
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up_raddr,
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up_rdata,
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up_rack);
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// parameters
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parameter CHID = 32'h0;
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parameter IQSEL = 0;
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parameter DP_DISABLE = 0;
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localparam PRBS_SEL = CHID;
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localparam PRBS_P09 = 0;
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localparam PRBS_P11 = 1;
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localparam PRBS_P15 = 2;
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localparam PRBS_P20 = 3;
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// dac interface
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input dac_clk;
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input dac_rst;
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input dac_valid;
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input [15:0] dma_data;
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input [11:0] adc_data;
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output [11:0] dac_data;
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output [11:0] dac_data_out;
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input [11:0] dac_data_in;
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// processor interface
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output dac_enable;
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input dac_data_sync;
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input dac_dds_format;
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// bus interface
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input up_rstn;
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input up_clk;
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input up_wreq;
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input [13:0] up_waddr;
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input [31:0] up_wdata;
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output up_wack;
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input up_rreq;
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input [13:0] up_raddr;
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output [31:0] up_rdata;
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output up_rack;
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// internal registers
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reg dac_valid_sel = 'd0;
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reg dac_enable = 'd0;
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reg [11:0] dac_data = 'd0;
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reg [11:0] dac_data_out = 'd0;
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reg [23:0] dac_pn_seq = 'd0;
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reg [11:0] dac_pn_data = 'd0;
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reg [15:0] dac_pat_data = 'd0;
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reg [15:0] dac_dds_phase_0 = 'd0;
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reg [15:0] dac_dds_phase_1 = 'd0;
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reg [15:0] dac_dds_incr_0 = 'd0;
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reg [15:0] dac_dds_incr_1 = 'd0;
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reg [15:0] dac_dds_data = 'd0;
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// internal signals
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wire dac_iqcor_valid_s;
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wire [15:0] dac_iqcor_data_s;
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wire [15:0] dac_dds_data_s;
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wire [15:0] dac_dds_scale_1_s;
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wire [15:0] dac_dds_init_1_s;
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wire [15:0] dac_dds_incr_1_s;
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wire [15:0] dac_dds_scale_2_s;
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wire [15:0] dac_dds_init_2_s;
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wire [15:0] dac_dds_incr_2_s;
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wire [15:0] dac_pat_data_1_s;
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wire [15:0] dac_pat_data_2_s;
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wire [ 3:0] dac_data_sel_s;
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wire dac_iqcor_enb_s;
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wire [15:0] dac_iqcor_coeff_1_s;
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wire [15:0] dac_iqcor_coeff_2_s;
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// standard prbs functions
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function [23:0] pn1fn;
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input [23:0] din;
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reg [23:0] dout;
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begin
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case (PRBS_SEL)
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PRBS_P09: begin
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dout[23] = din[ 8] ^ din[ 4];
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dout[22] = din[ 7] ^ din[ 3];
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dout[21] = din[ 6] ^ din[ 2];
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dout[20] = din[ 5] ^ din[ 1];
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dout[19] = din[ 4] ^ din[ 0];
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dout[18] = din[ 3] ^ din[ 8] ^ din[ 4];
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dout[17] = din[ 2] ^ din[ 7] ^ din[ 3];
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dout[16] = din[ 1] ^ din[ 6] ^ din[ 2];
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dout[15] = din[ 0] ^ din[ 5] ^ din[ 1];
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dout[14] = din[ 8] ^ din[ 0];
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dout[13] = din[ 7] ^ din[ 8] ^ din[ 4];
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dout[12] = din[ 6] ^ din[ 7] ^ din[ 3];
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dout[11] = din[ 5] ^ din[ 6] ^ din[ 2];
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dout[10] = din[ 4] ^ din[ 5] ^ din[ 1];
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dout[ 9] = din[ 3] ^ din[ 4] ^ din[ 0];
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dout[ 8] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
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dout[ 7] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
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dout[ 6] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
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dout[ 5] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
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dout[ 4] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
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dout[ 3] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
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dout[ 2] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
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dout[ 1] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
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dout[ 0] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
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end
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PRBS_P11: begin
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dout[23] = din[10] ^ din[ 8];
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dout[22] = din[ 9] ^ din[ 7];
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dout[21] = din[ 8] ^ din[ 6];
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dout[20] = din[ 7] ^ din[ 5];
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dout[19] = din[ 6] ^ din[ 4];
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dout[18] = din[ 5] ^ din[ 3];
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dout[17] = din[ 4] ^ din[ 2];
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dout[16] = din[ 3] ^ din[ 1];
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dout[15] = din[ 2] ^ din[ 0];
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dout[14] = din[ 1] ^ din[10] ^ din[ 8];
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dout[13] = din[ 0] ^ din[ 9] ^ din[ 7];
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dout[12] = din[10] ^ din[ 6];
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dout[11] = din[ 9] ^ din[ 5];
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dout[10] = din[ 8] ^ din[ 4];
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dout[ 9] = din[ 7] ^ din[ 3];
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dout[ 8] = din[ 6] ^ din[ 2];
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dout[ 7] = din[ 5] ^ din[ 1];
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dout[ 6] = din[ 4] ^ din[ 0];
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dout[ 5] = din[ 3] ^ din[10] ^ din[ 8];
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dout[ 4] = din[ 2] ^ din[ 9] ^ din[ 7];
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dout[ 3] = din[ 1] ^ din[ 8] ^ din[ 6];
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dout[ 2] = din[ 0] ^ din[ 7] ^ din[ 5];
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dout[ 1] = din[10] ^ din[ 6] ^ din[ 8] ^ din[ 4];
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dout[ 0] = din[ 9] ^ din[ 5] ^ din[ 7] ^ din[ 3];
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end
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PRBS_P15: begin
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dout[23] = din[14] ^ din[13];
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dout[22] = din[13] ^ din[12];
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dout[21] = din[12] ^ din[11];
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dout[20] = din[11] ^ din[10];
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dout[19] = din[10] ^ din[ 9];
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dout[18] = din[ 9] ^ din[ 8];
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dout[17] = din[ 8] ^ din[ 7];
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dout[16] = din[ 7] ^ din[ 6];
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dout[15] = din[ 6] ^ din[ 5];
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dout[14] = din[ 5] ^ din[ 4];
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dout[13] = din[ 4] ^ din[ 3];
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dout[12] = din[ 3] ^ din[ 2];
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dout[11] = din[ 2] ^ din[ 1];
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dout[10] = din[ 1] ^ din[ 0];
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dout[ 9] = din[ 0] ^ din[14] ^ din[13];
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dout[ 8] = din[14] ^ din[12];
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dout[ 7] = din[13] ^ din[11];
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dout[ 6] = din[12] ^ din[10];
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dout[ 5] = din[11] ^ din[ 9];
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dout[ 4] = din[10] ^ din[ 8];
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dout[ 3] = din[ 9] ^ din[ 7];
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dout[ 2] = din[ 8] ^ din[ 6];
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dout[ 1] = din[ 7] ^ din[ 5];
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dout[ 0] = din[ 6] ^ din[ 4];
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end
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PRBS_P20: begin
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dout[23] = din[19] ^ din[ 2];
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dout[22] = din[18] ^ din[ 1];
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dout[21] = din[17] ^ din[ 0];
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dout[20] = din[16] ^ din[19] ^ din[ 2];
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dout[19] = din[15] ^ din[18] ^ din[ 1];
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dout[18] = din[14] ^ din[17] ^ din[ 0];
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dout[17] = din[13] ^ din[16] ^ din[19] ^ din[ 2];
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dout[16] = din[12] ^ din[15] ^ din[18] ^ din[ 1];
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dout[15] = din[11] ^ din[14] ^ din[17] ^ din[ 0];
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dout[14] = din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
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dout[13] = din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
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dout[12] = din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
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dout[11] = din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
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dout[10] = din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
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dout[ 9] = din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
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dout[ 8] = din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
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dout[ 7] = din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
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dout[ 6] = din[ 2] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
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dout[ 5] = din[ 1] ^ din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
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dout[ 4] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
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dout[ 3] = din[19] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
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dout[ 2] = din[18] ^ din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
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dout[ 1] = din[17] ^ din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
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dout[ 0] = din[16] ^ din[ 2] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
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end
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endcase
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pn1fn = dout;
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end
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endfunction
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// global toggle
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always @(posedge dac_clk) begin
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if (dac_data_sync == 1'b1) begin
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dac_valid_sel <= 1'b0;
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end else if (dac_valid == 1'b1) begin
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dac_valid_sel <= ~dac_valid_sel;
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end
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end
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// dac iq correction
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always @(posedge dac_clk) begin
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dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
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if (dac_iqcor_valid_s == 1'b1) begin
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dac_data <= dac_iqcor_data_s[15:4];
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end
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end
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generate
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if (DP_DISABLE == 1) begin
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assign dac_iqcor_valid_s = dac_valid;
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assign dac_iqcor_data_s = {dac_data_out, 4'd0};
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end else begin
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ad_iqcor #(.IQSEL (IQSEL)) i_ad_iqcor (
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.clk (dac_clk),
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.valid (dac_valid),
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.data_in ({dac_data_out, 4'd0}),
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.data_iq ({dac_data_in, 4'd0}),
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.valid_out (dac_iqcor_valid_s),
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.data_out (dac_iqcor_data_s),
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.iqcor_enable (dac_iqcor_enb_s),
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.iqcor_coeff_1 (dac_iqcor_coeff_1_s),
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.iqcor_coeff_2 (dac_iqcor_coeff_2_s));
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end
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endgenerate
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// dac mux
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always @(posedge dac_clk) begin
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case (dac_data_sel_s)
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4'h9: dac_data_out <= dac_pn_data;
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4'h8: dac_data_out <= adc_data;
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4'h3: dac_data_out <= 12'd0;
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4'h2: dac_data_out <= dma_data[15:4];
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4'h1: dac_data_out <= dac_pat_data[15:4];
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default: dac_data_out <= dac_dds_data[15:4];
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endcase
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end
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// prbs sequences
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always @(posedge dac_clk) begin
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if (dac_data_sync == 1'b1) begin
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dac_pn_seq <= 24'hffffff;
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dac_pn_data <= 12'd0;
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end else if (dac_valid == 1'b1) begin
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if (dac_valid_sel == 1'b1) begin
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dac_pn_seq <= pn1fn(dac_pn_seq);
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dac_pn_data <= dac_pn_seq[11: 0];
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end else begin
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dac_pn_seq <= dac_pn_seq;
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dac_pn_data <= dac_pn_seq[23:12];
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end
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end
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end
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// pattern
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always @(posedge dac_clk) begin
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if (dac_valid == 1'b1) begin
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if (dac_valid_sel == 1'b0) begin
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dac_pat_data <= dac_pat_data_1_s;
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end else begin
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dac_pat_data <= dac_pat_data_2_s;
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end
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end
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end
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// dds
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always @(posedge dac_clk) begin
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if (dac_data_sync == 1'b1) begin
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dac_dds_phase_0 <= dac_dds_init_1_s;
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dac_dds_phase_1 <= dac_dds_init_2_s;
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dac_dds_incr_0 <= dac_dds_incr_1_s;
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dac_dds_incr_1 <= dac_dds_incr_2_s;
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dac_dds_data <= 16'd0;
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end else if (dac_valid == 1'b1) begin
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dac_dds_phase_0 <= dac_dds_phase_0 + dac_dds_incr_0;
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dac_dds_phase_1 <= dac_dds_phase_1 + dac_dds_incr_1;
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dac_dds_incr_0 <= dac_dds_incr_0;
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dac_dds_incr_1 <= dac_dds_incr_1;
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dac_dds_data <= dac_dds_data_s;
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end
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end
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// dds
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generate
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if (DP_DISABLE == 1) begin
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assign dac_dds_data_s = 16'd0;
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end else begin
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ad_dds i_dds (
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.clk (dac_clk),
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.dds_format (dac_dds_format),
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.dds_phase_0 (dac_dds_phase_0),
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.dds_scale_0 (dac_dds_scale_1_s),
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.dds_phase_1 (dac_dds_phase_1),
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.dds_scale_1 (dac_dds_scale_2_s),
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.dds_data (dac_dds_data_s));
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end
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endgenerate
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// single channel processor
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up_dac_channel #(.PCORE_DAC_CHID(CHID)) i_up_dac_channel (
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.dac_clk (dac_clk),
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.dac_rst (dac_rst),
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.dac_dds_scale_1 (dac_dds_scale_1_s),
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.dac_dds_init_1 (dac_dds_init_1_s),
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.dac_dds_incr_1 (dac_dds_incr_1_s),
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.dac_dds_scale_2 (dac_dds_scale_2_s),
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.dac_dds_init_2 (dac_dds_init_2_s),
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.dac_dds_incr_2 (dac_dds_incr_2_s),
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.dac_pat_data_1 (dac_pat_data_1_s),
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.dac_pat_data_2 (dac_pat_data_2_s),
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.dac_data_sel (dac_data_sel_s),
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.dac_iqcor_enb (dac_iqcor_enb_s),
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.dac_iqcor_coeff_1 (dac_iqcor_coeff_1_s),
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.dac_iqcor_coeff_2 (dac_iqcor_coeff_2_s),
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.up_usr_datatype_be (),
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.up_usr_datatype_signed (),
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.up_usr_datatype_shift (),
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.up_usr_datatype_total_bits (),
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.up_usr_datatype_bits (),
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.up_usr_interpolation_m (),
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.up_usr_interpolation_n (),
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.dac_usr_datatype_be (1'b0),
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|
.dac_usr_datatype_signed (1'b1),
|
|
.dac_usr_datatype_shift (8'd0),
|
|
.dac_usr_datatype_total_bits (8'd16),
|
|
.dac_usr_datatype_bits (8'd16),
|
|
.dac_usr_interpolation_m (16'd1),
|
|
.dac_usr_interpolation_n (16'd1),
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_wreq (up_wreq),
|
|
.up_waddr (up_waddr),
|
|
.up_wdata (up_wdata),
|
|
.up_wack (up_wack),
|
|
.up_rreq (up_rreq),
|
|
.up_raddr (up_raddr),
|
|
.up_rdata (up_rdata),
|
|
.up_rack (up_rack));
|
|
|
|
endmodule
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|
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// ***************************************************************************
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// ***************************************************************************
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