771 lines
29 KiB
ReStructuredText
771 lines
29 KiB
ReStructuredText
.. _ad9081_fmca_ebz:
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AD9081-FMCA-EBZ/AD9082-FMCA-EBZ HDL project
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===============================================================================
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Overview
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-------------------------------------------------------------------------------
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The :adi:`AD9081-FMCA-EBZ <EVAL-AD9081>` / :adi:`AD9082-FMCA-EBZ <EVAL-AD9082>`
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reference design (also known as Single MxFE) is a processor based
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(e.g. Microblaze) embedded system.
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The design consists from a receive and a transmit chain.
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The receive chain transports the captured samples from ADC to the system
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memory (DDR). Before transferring the data to DDR the samples are stored
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in a buffer implemented on block rams from the FPGA fabric
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(util_adc_fifo). The space allocated in the buffer for each channel
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depends on the number of currently active channels. It goes up to M x
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64k samples if a single channel is selected or 64k samples per channel
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if all channels are selected.
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The transmit chain transports samples from the system memory to the DAC
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devices. Before streaming out the data to the DAC through the JESD link
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the samples first are loaded into a buffer (util_dac_fifo) which will
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cyclically stream the samples at the tx_device_clk data rate. The space
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allocated in the transmit buffer for each channel depends on the number
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of currently active channels. It goes up to M x 64k samples if a single
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channel is selected or 64k samples per channel if all channels are
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selected.
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All cores from the receive and transmit chains are programmable through
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an AXI-Lite interface.
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The transmit and receive chains can operate at different data rates
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having separate rx_device_clk/tx_device_clk and corresponding lane rates
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but must share the same reference clock.
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Supported boards
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-------------------------------------------------------------------------------
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- :adi:`AD9081-FMCA-EBZ <EVAL-AD9081>`
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- :adi:`AD9082-FMCA-EBZ <EVAL-AD9082>`
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Supported devices
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-------------------------------------------------------------------------------
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- :adi:`AD9081`
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- :adi:`AD9082`
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- :adi:`AD9177`
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- :adi:`AD9207`
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- :adi:`AD9209`
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- :adi:`AD9986`
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- :adi:`AD9988`
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Supported carriers
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-------------------------------------------------------------------------------
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.. list-table::
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:widths: 35 35 30
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:header-rows: 1
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* - Evaluation board
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- Carrier
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- FMC slot
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* - :adi:`AD9081-FMCA-EBZ <EVAL-AD9081>`
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- `A10SoC`_
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- FMCA
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* -
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- :xilinx:`VCK190`
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- FMC0
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* -
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- :xilinx:`VCU118`
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- FMC+
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* -
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- :xilinx:`VCU128`
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- FMC+
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* -
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- :xilinx:`ZCU102`
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- FMC HPC0
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* -
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- :xilinx:`ZC706`
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- FMC HPC
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.. list-table::
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:widths: 35 35 30
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:header-rows: 1
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* - Evaluation board
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- Carrier
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- FMC slot
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* - :adi:`AD9082-FMCA-EBZ <EVAL-AD9082>`
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- :xilinx:`VCK190`
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- FMC0
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* -
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- :xilinx:`VCU118`
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- FMC+
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* -
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- :xilinx:`ZCU102`
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- FMC HPC0
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* -
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- :xilinx:`ZC706`
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- FMC HPC
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Block design
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-------------------------------------------------------------------------------
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Block diagram
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The data path and clock domains are depicted in the below diagrams:
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Example block design for Single link; M=8; L=4
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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.. image:: ad9081_204b_M8L4.svg
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:width: 800
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:align: center
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:alt: AD9081-FMCA-EBZ JESD204B M=8 L=4 block diagram
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The Rx links (ADC Path) operate with the following parameters:
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- Rx Deframer parameters: L=4, M=8, F=4, S=1, NP=16, N=16 (Quick
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Config 0x0A)
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- Sample Rate: 250 MSPS
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- Dual link: No
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- RX_DEVICE_CLK: 250 MHz (Lane Rate/40)
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- REF_CLK: 500MHz (Lane Rate/20)
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- JESD204B Lane Rate: 10Gbps
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- QPLL0 or CPLL
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The Tx links (DAC Path) operate with the following parameters:
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- Tx Framer parameters: L=4, M=8, F=4, S=1, NP=16, N=16 (Quick Config
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0x09)
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- Sample Rate: 250 MSPS
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- Dual link: No
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- TX_DEVICE_CLK: 250 MHz (Lane Rate/40)
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- REF_CLK: 500MHz (Lane Rate/20)
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- JESD204B Lane Rate: 10Gbps
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- QPLL0 or CPLL
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Example block design for Single link; M=4; L=8
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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.. image:: ad9081_204b_M4L8.svg
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:width: 800
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:align: center
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:alt: AD9081-FMCA-EBZ JESD204B M=4 L=8 block diagram
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The Rx links are set for full bandwidth mode and operate with the
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following parameters:
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- Rx Deframer parameters: L=8, M=4, F=1, S=1, NP=16, N=16 (Quick
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Config 0x12)
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- Sample Rate: 1550 MSPS
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- Dual link: No
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- RX_DEVICE_CLK: 387.5 MHz (Lane Rate/40)
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- REF_CLK: 775MHz (Lane Rate/20)
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- JESD204B Lane Rate: 15.5Gbps
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- QPLL0
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The Tx links are set for full bandwidth mode and operate with the
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following parameters:
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- Tx Framer parameters: L=8, M=4, F=1, S=1, NP=16, N=16 (Quick Config
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0x11)
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- Sample Rate: 1550 MSPS
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- Dual link: No
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- TX_DEVICE_CLK: 387.5 MHz (Lane Rate/40)
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- REF_CLK: 775MHz (Lane Rate/20)
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- JESD204B Lane Rate: 15.5Gbps
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- QPLL0
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Example block design for Single link; M=2; L=8; JESD204C
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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.. note::
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In 2019_R2 release, the AMD JESD Physical layer IP Core is used,
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however in newer versions it is replaced with ADI's util_adxcvr IP core.
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.. image:: ad9081_204c_M2L8.svg
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:width: 800
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:align: center
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:alt: AD9081-FMCA-EBZ JESD204C M=2 L=8 block diagram
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.. warning::
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**Build instructions:**
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The project must be built with the following parameters:
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.. code-block:: bash
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make JESD_MODE=64B66B \
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RX_RATE=16.5 \
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TX_RATE=16.5 \
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RX_JESD_M=2 \
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RX_JESD_L=8 \
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RX_JESD_S=2 \
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RX_JESD_NP=16 \
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TX_JESD_M=2 \
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TX_JESD_L=8 \
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TX_JESD_S=4 \
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TX_JESD_NP=8
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The Rx link is operating with the following parameters:
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- Rx Deframer parameters: L=8, M=2, F=1, S=2, NP=16, N=16 (Quick Config
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0x13)
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- Sample Rate: 4000 MSPS
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- Dual link: No
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- RX_DEVICE_CLK: 250 MHz (Lane Rate/66)
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- REF_CLK: 500 MHz (Lane Rate/33)
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- JESD204C Lane Rate: 16.5Gbps
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- QPLL1
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The Tx link is operating with the following parameters:
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- Tx Framer parameters: L=8, M=2, F=1, S=4, NP=8, N=8 (Quick Config
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0x13)
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- Sample Rate: 8000 MSPS
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- Dual link: No
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- TX_DEVICE_CLK: 250 MHz (Lane Rate/66)
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- REF_CLK: 500 MHz (Lane Rate/33)
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- JESD204C Lane Rate: 16.5Gbps
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- QPLL1
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Configuration modes
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The block design supports configuration of parameters and scales.
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We have listed a couple of examples at section
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`Building the HDL project`_ and the default modes
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for each project.
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.. note::
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The parameters for Rx or Tx links can be changed from the
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**system_project.tcl** file, located in
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hdl/projects/ad9081_fmca_ebz/$CARRIER/system_project.tcl
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.. warning::
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``Lane Rate = I/Q Sample Rate x M x N' x (10 \ 8) \ L``
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The following are the parameters of this project that can be configured:
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- JESD_MODE: used link layer encoder mode
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- 64B66B - 64b66b link layer defined in JESD204C, uses AMD IP as Physical
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Layer
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- 8B10B - 8b10b link layer defined in JESD204B, uses ADI IP as Physical
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Layer
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- RX_LANE_RATE: lane rate of the Rx link (MxFE to FPGA)
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- TX_LANE_RATE: lane rate of the Tx link (FPGA to MxFE)
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- REF_CLK_RATE: the rate of the reference clock
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- [RX/TX]_JESD_M: number of converters per link
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- [RX/TX]_JESD_L: number of lanes per link
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- [RX/TX]_JESD_S: number of samples per frame
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- [RX/TX]_JESD_NP: number of bits per sample
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- [RX/TX]_NUM_LINKS: number of links
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- [RX/TX]_TPL_WIDTH
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- TDD_SUPPORT: set to 1, adds the TDD; enables external synchronization through TDD. Must be set to 1 when SHARED_DEVCLK=1
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- SHARED_DEVCLK
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- TDD_CHANNEL_CNT
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- TDD_SYNC_WIDTH
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- TDD_SYNC_INT
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- TDD_SYNC_EXT
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- TDD_SYNC_EXT_CDC: if enabled, the CDC circuitry for the external sync signal is added
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- [RX/TX]_KS_PER_CHANNEL: Number of samples stored in internal buffers in
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kilosamples per converter (M)
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- [ADC/DAC]_DO_MEM_TYPE
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- Check out this guide on more details regarding these parameters:
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:dokuwiki:`resources/fpga/docs/axi_tdd`
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Clock scheme
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The clock sources depend on the carrier that is used:
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:xilinx:`ZCU102`
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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.. image:: ad9081_clock_scheme_zcu102.svg
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:width: 800
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:align: center
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:alt: AD9081-FMCA-EBZ ZCU102 clock scheme
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:xilinx:`VCU118`
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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.. image:: ad9081_clock_scheme_vcu118.svg
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:width: 800
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:align: center
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:alt: AD9081-FMCA-EBZ VCU118 clock scheme
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Limitations
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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.. warning::
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For the parameter selection, the following restrictions apply:
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- NP = 8, 12, 16
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- F = 1, 2, 3, 4, 6, 8
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- https://wiki.analog.com/resources/fpga/peripherals/jesd204/axi_jesd204_rx#restrictions
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- https://wiki.analog.com/resources/fpga/peripherals/jesd204/axi_jesd204_tx#restrictions
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CPU/Memory interconnects addresses
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The addresses are dependent on the architecture of the FPGA, having an offset
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added to the base address from HDL (see more at :ref:`architecture`).
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Depending on the values of parameters $INTF_CFG, $ADI_PHY_SEL and $TDD_SUPPORT,
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some IPs are instatiated and some are not.
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Check-out the table below to find out the conditions.
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==================== ================================= =============== =========== ============
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Instance Depends on parameter Zynq/Microblaze ZynqMP Versal
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==================== ================================= =============== =========== ============
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axi_mxfe_rx_xcvr $INTF_CFG!="TX" & $ADI_PHY_SEL==1 0x44A6_0000 0x84A6_0000 0xA4A6_00000
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rx_mxfe_tpl_core $INTF_CFG!="TX" 0x44A1_0000 0x84A1_0000 0xA4A1_00000
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axi_mxfe_rx_jesd $INTF_CFG!="TX" 0x44A9_0000 0x84A9_0000 0xA4A9_00000
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axi_mxfe_rx_dma $INTF_CFG!="TX" 0x7C42_0000 0x9C42_0000 0xBC42_00000
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mxfe_rx_data_offload $INTF_CFG!="TX" 0x7C45_0000 0x9C45_0000 0xBC45_00000
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axi_mxfe_tx_xcvr $INTF_CFG!="RX" & $ADI_PHY_SEL==1 0x44B6_0000 0x84B6_0000 0xA4B6_00000
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tx_mxfe_tpl_core $INTF_CFG!="RX" 0x44B1_0000 0x84B1_0000 0xA4B1_00000
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axi_mxfe_tx_jesd $INTF_CFG!="RX" 0x44B9_0000 0x84B9_0000 0xA4B9_00000
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axi_mxfe_tx_dma $INTF_CFG!="RX" 0x7C43_0000 0x9C43_0000 0xBC43_00000
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mxfe_tx_data_offload $INTF_CFG!="RX" 0x7C44_0000 0x9C44_0000 0xBC44_00000
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axi_tdd_0 $TDD_SUPPORT==1 0x7C46_0000 0x9C46_0000 0xBC46_00000
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==================== ================================= =============== =========== ============
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SPI connections
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. list-table::
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:widths: 25 25 25 25
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:header-rows: 1
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* - SPI type
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- SPI manager instance
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- SPI subordinate
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- CS
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* - PS
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- spi0
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- AD9081
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- 0
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* - PS
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- spi1
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- HMC7044
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- 0
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GPIOs
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. list-table::
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:widths: 25 20 20 20 15
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:header-rows: 2
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* - GPIO signal
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- Direction
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- HDL GPIO EMIO
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- Software GPIO
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- Software GPIO
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* -
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- (from FPGA view)
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-
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- Zynq-7000
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- Zynq MP
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* - txen[1:0]
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- OUT
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- 59:58
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- 113:112
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- 137:136
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* - rxen[1:0]
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- OUT
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- 57:56
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- 111:110
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- 135:134
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* - rstb
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- OUT
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- 55
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- 109
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- 133
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* - hmc_sync
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- OUT
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- 54
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- 108
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- 132
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* - irqb[1:0]
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- IN
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- 53:52
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- 107:106
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- 131:130
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* - agc3[1:0]
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- IN
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- 51:50
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- 105:104
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- 129:128
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* - agc2[1:0]
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- IN
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- 49:48
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- 103:102
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- 127:126
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* - agc1[1:0]
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- IN
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- 47:46
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- 101:100
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- 125:124
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* - agc0[1:0]
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- IN
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- 45:44
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- 99:98
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- 123:122
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* - hmc_gpio1
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- INOUT
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- 43
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- 97
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- 121
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* - gpio[10:0]
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- INOUT
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- 42:32
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- 96:86
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- 120:110
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Interrupts
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Below are the Programmable Logic interrupts used in this project.
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================ === ========== =========== ============ =============
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Instance name HDL Linux Zynq Actual Zynq Linux ZynqMP Actual ZynqMP
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================ === ========== =========== ============ =============
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axi_mxfe_rx_dma 13 57 89 109 141
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axi_mxfe_tx_dma 12 56 88 108 140
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axi_mxfe_rx_jesd 11 55 87 107 139
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axi_mxfe_tx_jesd 10 54 86 106 138
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================ === ========== =========== ============ =============
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Building the HDL project
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-------------------------------------------------------------------------------
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The design is built upon ADI's generic HDL reference design framework.
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ADI does not distribute the bit/elf files of these projects so they
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must be built from the sources available :git-hdl:`here </>`. To get
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the source you must
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`clone <https://git-scm.com/book/en/v2/Git-Basics-Getting-a-Git-Repository>`__
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the HDL repository.
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Then go to the :git-hdl:`projects/ad9081_fmca_ebz <projects/ad9081_fmca_ebz>`
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location and run the make command by typing in your command prompt:
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**Linux/Cygwin/WSL**
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.. code-block::
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:linenos:
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:emphasize-lines: 2, 6
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user@analog:~$ cd hdl/projects/ad9081_fmca_ebz/zcu102
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// these are just examples of how to write the *make* command with parameters
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user@analog:~/hdl/projects/ad9081_fmca_ebz/zcu102$ make parameter1=value parameter2=value
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user@analog:~$ cd hdl/projects/ad9081_fmca_ebz/a10soc
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// these are just examples of how to write the *make* command with parameters
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user@analog:~/hdl/projects/ad9081_fmca_ebz/a10soc$ make RX_LANE_RATE=2.5 TX_LANE_RATE=2.5 RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1 RX_JESD_NP=16 TX_JESD_L=8 TX_JESD_M=4 TX_JESD_S=1 TX_JESD_NP=16
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The following dropdowns contain tables with the parameters that can be used to
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configure this project, depending on the carrier used.
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Where a cell contains a --- (dash) it means that the parameter doesn't exist
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for that project (ad9081_fmca_ebz/carrier or ad9082_fmca_ebz/carrier).
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.. warning::
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For the parameter selection, the following restrictions apply:
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- NP = 8, 12, 16
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- F = 1, 2, 3, 4, 6, 8
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- https://wiki.analog.com/resources/fpga/peripherals/jesd204/axi_jesd204_rx#restrictions
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- https://wiki.analog.com/resources/fpga/peripherals/jesd204/axi_jesd204_tx#restrictions
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``NP`` notation is equivalent with ``N'``
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.. collapsible:: Default values of the ``make`` parameters for AD9081-FMCA-EBZ
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+-------------------+------------------------------------------------------+
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| Parameter | Default value of the parameters depending on carrier |
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| +----------+--------+--------+--------+-------+--------+
|
|
| | A10SoC | VCK190 | VCU118 | VCU128 | ZC706 | ZCU102 |
|
|
+===================+==========+========+========+========+=======+========+
|
|
| JESD_MODE | --- | 64B66B | 8B10B | 8B10B | 8B10B | 8B10B|
|
|
+-------------------+----------+--------+--------+--------+-------+--------+
|
|
| RX_LANE_RATE | 10 | 24.75 | 10 | 10 | 10 | 10 |
|
|
+-------------------+----------+--------+--------+--------+-------+--------+
|
|
| TX_LANE_RATE | 10 | 24.75 | 10 | 10 | 10 | 10 |
|
|
+-------------------+----------+--------+--------+--------+-------+--------+
|
|
| REF_CLK_RATE | --- | 375 | --- | --- | --- | --- |
|
|
+-------------------+----------+--------+--------+--------+-------+--------+
|
|
| RX_JESD_M | 8 | 8 | 8 | 8 | 8 | 8 |
|
|
+-------------------+----------+--------+--------+--------+-------+--------+
|
|
| RX_JESD_L | 4 | 8 | 4 | 4 | 4 | 4 |
|
|
+-------------------+----------+--------+--------+--------+-------+--------+
|
|
| RX_JESD_S | 1 | 2 | 1 | 1 | 1 | 1 |
|
|
+-------------------+----------+--------+--------+--------+-------+--------+
|
|
| RX_JESD_NP | 16 | 12 | 16 | 16 | 16 | 16 |
|
|
+-------------------+----------+--------+--------+--------+-------+--------+
|
|
| RX_NUM_LINKS | 1 | 1 | 1 | 1 | 1 | 1 |
|
|
+-------------------+----------+--------+--------+--------+-------+--------+
|
|
| RX_TPL_WIDTH | --- | --- | --- | --- | --- | {} |
|
|
+-------------------+----------+--------+--------+--------+-------+--------+
|
|
| TX_JESD_M | 8 | 8 | 8 | 8 | 8 | 8 |
|
|
+-------------------+----------+--------+--------+--------+-------+--------+
|
|
| TX_JESD_L | 4 | 8 | 4 | 4 | 4 | 4 |
|
|
+-------------------+----------+--------+--------+--------+-------+--------+
|
|
| TX_JESD_S | 1 | 2 | 1 | 1 | 1 | 1 |
|
|
+-------------------+----------+--------+--------+--------+-------+--------+
|
|
| TX_JESD_NP | 16 | 12 | 16 | 16 | 16 | 16 |
|
|
+-------------------+----------+--------+--------+--------+-------+--------+
|
|
| TX_NUM_LINKS | 1 | 1 | 1 | 1 | 1 | 1 |
|
|
+-------------------+----------+--------+--------+--------+-------+--------+
|
|
| TX_TPL_WIDTH | --- | --- | --- | --- | --- | {} |
|
|
+-------------------+----------+--------+--------+--------+-------+--------+
|
|
| TDD_SUPPORT | --- | --- | --- | --- | --- | 0 |
|
|
+-------------------+----------+--------+--------+--------+-------+--------+
|
|
| SHARED_DEVCLK | --- | --- | --- | --- | --- | 0 |
|
|
+-------------------+----------+--------+--------+--------+-------+--------+
|
|
| TDD_CHANNEL_CNT | --- | --- | --- | --- | --- | 2 |
|
|
+-------------------+----------+--------+--------+--------+-------+--------+
|
|
| TDD_SYNC_WIDTH | --- | --- | --- | --- | --- | 32 |
|
|
+-------------------+----------+--------+--------+--------+-------+--------+
|
|
| TDD_SYNC_INT | --- | --- | --- | --- | --- | 1 |
|
|
+-------------------+----------+--------+--------+--------+-------+--------+
|
|
| TDD_SYNC_EXT | --- | --- | --- | --- | --- | 0 |
|
|
+-------------------+----------+--------+--------+--------+-------+--------+
|
|
| TDD_SYNC_EXT_CDC | --- | --- | --- | --- | --- | 0 |
|
|
+-------------------+----------+--------+--------+--------+-------+--------+
|
|
| RX_KS_PER_CHANNEL | 32 | 64 | 64 | 16384 | --- | --- |
|
|
+-------------------+----------+--------+--------+--------+-------+--------+
|
|
| TX_KS_PER_CHANNEL | 32 | 64 | 64 | 16384 | --- | --- |
|
|
+-------------------+----------+--------+--------+--------+-------+--------+
|
|
| ADC_DO_MEM_TYPE | --- | --- | --- | 2 | --- | --- |
|
|
+-------------------+----------+--------+--------+--------+-------+--------+
|
|
| DAC_DO_MEM_TYPE | --- | --- | --- | 2 | --- | --- |
|
|
+-------------------+----------+--------+--------+--------+-------+--------+
|
|
|
|
.. collapsible:: Default values of the ``make`` parameters for AD9082-FMCA-EBZ
|
|
|
|
+-------------------+-----------------------------------------------+
|
|
| Parameter | Default value of the parameters |
|
|
| | depending on carrier |
|
|
| +--------+--------+--------------+--------------+
|
|
| | VCK190 | VCU118 | ZC706 | ZCU102 |
|
|
+===================+========+========+==============+==============+
|
|
| JESD_MODE | 64B66B | 8B10B | :red:`8B10B*`| :red:`8B10B*`|
|
|
+-------------------+--------+--------+--------------+--------------+
|
|
| RX_LANE_RATE | 24.75 | 15 | 10 | 15 |
|
|
+-------------------+--------+--------+--------------+--------------+
|
|
| TX_LANE_RATE | 24.75 | 15 | 10 | 15 |
|
|
+-------------------+--------+--------+--------------+--------------+
|
|
| REF_CLK_RATE | 375 | --- | --- | --- |
|
|
+-------------------+--------+--------+--------------+--------------+
|
|
| RX_JESD_M | 4 | 4 | 8 | 4 |
|
|
+-------------------+--------+--------+--------------+--------------+
|
|
| RX_JESD_L | 8 | 8 | 4 | 8 |
|
|
+-------------------+--------+--------+--------------+--------------+
|
|
| RX_JESD_S | 4 | 1 | 1 | 1 |
|
|
+-------------------+--------+--------+--------------+--------------+
|
|
| RX_JESD_NP | 12 | 16 | 16 | 16 |
|
|
+-------------------+--------+--------+--------------+--------------+
|
|
| RX_NUM_LINKS | 1 | 1 | 1 | 1 |
|
|
+-------------------+--------+--------+--------------+--------------+
|
|
| RX_TPL_WIDTH | --- | --- | --- | {} |
|
|
+-------------------+--------+--------+--------------+--------------+
|
|
| TX_JESD_M | 4 | 4 | 8 | 4 |
|
|
+-------------------+--------+--------+--------------+--------------+
|
|
| TX_JESD_L | 8 | 8 | 4 | 8 |
|
|
+-------------------+--------+--------+--------------+--------------+
|
|
| TX_JESD_S | 8 | 1 | 1 | 1 |
|
|
+-------------------+--------+--------+--------------+--------------+
|
|
| TX_JESD_NP | 12 | 16 | 16 | 16 |
|
|
+-------------------+--------+--------+--------------+--------------+
|
|
| TX_NUM_LINKS | 1 | 1 | 1 | 1 |
|
|
+-------------------+--------+--------+--------------+--------------+
|
|
| TX_TPL_WIDTH | --- | --- | --- | {} |
|
|
+-------------------+--------+--------+--------------+--------------+
|
|
| RX_KS_PER_CHANNEL | 64 | 64 | --- | --- |
|
|
+-------------------+--------+--------+--------------+--------------+
|
|
| TX_KS_PER_CHANNEL | 64 | 64 | --- | --- |
|
|
+-------------------+--------+--------+--------------+--------------+
|
|
|
|
.. warning::
|
|
|
|
``*`` --- for this carrier only the 8B10B mode is supported
|
|
|
|
The result of the build, if parameters were used, will be in a folder named
|
|
by the configuration used:
|
|
|
|
if the following command was run
|
|
|
|
``make RX_LANE_RATE=2.5 TX_LANE_RATE=2.5 RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1 RX_JESD_NP=16 TX_JESD_L=8 TX_JESD_M=4 TX_JESD_S=1 TX_JESD_NP=16``
|
|
|
|
then the folder name will be:
|
|
|
|
``RXRATE2_5_TXRATE2_5_RXL8_RXM4_RXS1_RXNP16_TXL8_TXM4_TXS1_TXNP16``
|
|
because of truncation of some keywords so the name will not exceed the limits
|
|
of the Operating System (``JESD``, ``LANE``, etc. are removed) of 260
|
|
characters.
|
|
|
|
A more comprehensive build guide can be found in the :ref:`build_hdl` user guide.
|
|
|
|
Software considerations
|
|
-------------------------------------------------------------------------------
|
|
|
|
ADC - crossbar config
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
|
Due to physical constraints, Rx lanes are reordered as described in the
|
|
following table.
|
|
|
|
e.g physical lane 2 from ADC connects to logical lane 7
|
|
from the FPGA. Therefore the crossbar from the device must be set
|
|
accordingly.
|
|
|
|
============ ===========================
|
|
ADC phy Lane FPGA Rx lane / Logical Lane
|
|
============ ===========================
|
|
0 2
|
|
1 0
|
|
2 7
|
|
3 6
|
|
4 5
|
|
5 4
|
|
6 3
|
|
7 1
|
|
============ ===========================
|
|
|
|
DAC - crossbar config
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
|
Due to physical constraints, Tx lanes are reordered as described in the
|
|
following table.
|
|
|
|
e.g physical lane 2 from DAC connects to logical lane 7
|
|
from the FPGA. Therefore the crossbar from the device must be set
|
|
accordingly.
|
|
|
|
============ ===========================
|
|
DAC phy lane FPGA Tx lane / Logical lane
|
|
============ ===========================
|
|
0 0
|
|
1 2
|
|
2 7
|
|
3 6
|
|
4 1
|
|
5 5
|
|
6 4
|
|
7 3
|
|
============ ===========================
|
|
|
|
Resources
|
|
-------------------------------------------------------------------------------
|
|
|
|
Systems related
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
|
- :dokuwiki:`[Wiki] AD9081 & AD9082 & AD9988 & AD9986 Prototyping Platform User Guide <resources/eval/user-guides/ad9081_fmca_ebz>`
|
|
- Here you can find all the quick start guides on wiki documentation:dokuwiki:`[Wiki] AD9081 Quick Start Guides <resources/eval/user-guides/ad9081_fmca_ebz/quickstart>`
|
|
|
|
Here you can find the quick start guides available for these evaluation boards:
|
|
|
|
.. list-table::
|
|
:widths: 20 10 20 20 20 10
|
|
:header-rows: 1
|
|
|
|
* - Evaluation board
|
|
- Zynq-7000
|
|
- Zynq UltraScale+ MP
|
|
- Microblaze
|
|
- Versal
|
|
- Arria 10
|
|
* - AD9081/AD9082-FMCA-EBZ
|
|
- :dokuwiki:`ZC706 <resources/eval/user-guides/ad9081_fmca_ebz/quickstart/zynq>`
|
|
- :dokuwiki:`ZCU102 <resources/eval/user-guides/ad9081_fmca_ebz/quickstart/zynqmp>`
|
|
- :dokuwiki:`VCU118 <resources/eval/user-guides/ad9081_fmca_ebz/quickstart/microblaze>`
|
|
- :dokuwiki:`VCK190/VMK180 <resources/eval/user-guides/ad9081_fmca_ebz/quickstart/versal>`
|
|
- :dokuwiki:`A10SoC <resources/eval/user-guides/ad9081/quickstart/a10soc>`
|
|
|
|
Hardware related
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
|
- Product datasheets:
|
|
|
|
- :adi:`AD9081`
|
|
- :adi:`AD9082`
|
|
- :adi:`AD9988`
|
|
- :adi:`AD9986`
|
|
- `UG-1578, Device User Guide <https://www.analog.com/media/en/technical-documentation/user-guides/ad9081-ad9082-ug-1578.pdf>`__
|
|
- `UG-1829, Evaluation Board User Guide <https://www.analog.com/media/en/technical-documentation/user-guides/ad9081-fmca-ebz-9082-fmca-ebz-ug-1829.pdf>`__
|
|
|
|
HDL related
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
|
- :git-hdl:`AD9081_FMCA_EBZ HDL project source code <projects/ad9081_fmca_ebz>`
|
|
- :git-hdl:`AD9082_FMCA_EBZ HDL project source code <projects/ad9082_fmca_ebz>`
|
|
|
|
.. list-table::
|
|
:widths: 30 35 35
|
|
:header-rows: 1
|
|
|
|
* - IP name
|
|
- Source code link
|
|
- Documentation link
|
|
* - AXI_DMAC
|
|
- :git-hdl:`library/axi_dmac`
|
|
- :ref:`here <axi_dmac>`
|
|
* - AXI_SYSID
|
|
- :git-hdl:`library/axi_sysid`
|
|
- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_sysid>`
|
|
* - SYSID_ROM
|
|
- :git-hdl:`library/sysid_rom`
|
|
- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_sysid>`
|
|
* - UTIL_CPACK2
|
|
- :git-hdl:`library/util_pack/util_cpack2`
|
|
- :dokuwiki:`[Wiki] <resources/fpga/docs/util_cpack>`
|
|
* - UTIL_UPACK2
|
|
- :git-hdl:`library/util_pack/util_upack2`
|
|
- :dokuwiki:`[Wiki] <resources/fpga/docs/util_upack>`
|
|
* - UTIL_ADXCVR for AMD
|
|
- :git-hdl:`library/xilinx/util_adxcvr`
|
|
- :dokuwiki:`[Wiki] <resources/fpga/docs/util_xcvr>`
|
|
* - AXI_ADXCVR for Intel
|
|
- :git-hdl:`library/intel/axi_adxcvr`
|
|
- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_adxcvr>`
|
|
* - AXI_ADXCVR for AMD
|
|
- :git-hdl:`library/xilinx/axi_adxcvr`
|
|
- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_adxcvr>`
|
|
* - AXI_JESD204_RX
|
|
- :git-hdl:`library/jesd204/axi_jesd204_rx`
|
|
- :dokuwiki:`[Wiki] <resources/fpga/peripherals/jesd204/axi_jesd204_rx>`
|
|
* - AXI_JESD204_TX
|
|
- :git-hdl:`library/jesd204/axi_jesd204_tx`
|
|
- :dokuwiki:`[Wiki] <resources/fpga/peripherals/jesd204/axi_jesd204_tx>`
|
|
* - JESD204_TPL_ADC
|
|
- :git-hdl:`library/jesd204/ad_ip_jesd204_tpl_adc`
|
|
- :dokuwiki:`[Wiki] <resources/fpga/peripherals/jesd204/jesd204_tpl_adc>`
|
|
* - JESD204_TPL_DAC
|
|
- :git-hdl:`library/jesd204/ad_ip_jesd204_tpl_dac`
|
|
- :dokuwiki:`[Wiki] <resources/fpga/peripherals/jesd204/jesd204_tpl_dac>`
|
|
|
|
- :dokuwiki:`[Wiki] Generic JESD204B block designs <resources/fpga/docs/hdl/generic_jesd_bds>`
|
|
- :dokuwiki:`[Wiki] JESD204B High-Speed Serial Interface Support <resources/fpga/peripherals/jesd204>`
|
|
|
|
Software related
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
|
- :dokuwiki:`[Wiki] AD9081-FMCA-EBZ Linux driver wiki page <resources/tools-software/linux-drivers/iio-mxfe/ad9081>`
|
|
- Python support:
|
|
|
|
- `AD9081 class documentation <https://analogdevicesinc.github.io/pyadi-iio/devices/adi.ad9081.html>`__
|
|
- `PyADI-IIO documentation <https://analogdevicesinc.github.io/pyadi-iio/>`__
|
|
|
|
.. include:: ../common/more_information.rst
|
|
|
|
.. include:: ../common/support.rst
|
|
|
|
.. _A10SoC: https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/arria/10-sx.html
|