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Lars-Peter Clausen db459d96e9 daq2: zc706: Increase DAC FIFO size 
Currently the DAC FIFO size for the ZC706 DAQ2 project is 16kB. This is
quite a limiting size for practical applications. Increase the size to 1MB
to allow loading larger waveforms.

In this configuration the DAC FIFO will use half of the available BRAM
cells in the FPGA. This still leaves quite a few BRAMs available for
user application logic added to the design. If a user design should run out
of BRAMs nevertheless they can reduce the FIFO size, if not required by the
application, to free up some cells.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2017-04-28 11:34:45 +02:00
..
ad6676evb ad6676evb: Set default xcvr parameters to common design 2017-04-18 11:26:51 +03:00
ad7616_sdz updated makefiles 2016-12-09 23:06:41 +02:00
ad7768evb lib_refactoring: Update Make files 2016-08-08 16:38:38 +03:00
ad9265_fmc lib_refactoring: Update Make files 2016-08-08 16:38:38 +03:00
ad9434_fmc lib_refactoring: Update Make files 2016-08-08 16:38:38 +03:00
ad9467_fmc ad9467_fmc: Delete asynchronous clock group definition 2017-02-10 16:21:35 +02:00
ad9739a_fmc lib_refactoring: Update Make files 2016-08-08 16:38:38 +03:00
adrv9371x adrv9371x: Change the axi_adxcvr cores addresses 2017-01-19 15:23:03 +02:00
adv7511 adv7511: KCU105, updated system_top to remove part of the Warnings 2016-10-10 16:12:17 +03:00
arradio updated makefiles 2016-12-09 23:06:41 +02:00
cftl_cip lib_refactoring: Update Make files 2016-08-08 16:38:38 +03:00
cftl_std lib_refactoring: Update Make files 2016-08-08 16:38:38 +03:00
cn0363 cn0363: Microzed, updated system_top to remove part of the Warnings 2016-10-10 16:08:59 +03:00
common axi_dacfifo: Redesign the bypass functionality 2017-04-03 10:37:08 +03:00
daq1 projects/altera* - default & common qsys commands 2016-12-20 16:27:44 -05:00
daq2 daq2: zc706: Increase DAC FIFO size 2017-04-28 11:34:45 +02:00
daq3 daq3/a10gx/system_constr.sdc- fix typo 2017-02-03 09:26:07 -05:00
fmcadc2 fmcadc2: Move GT setting to common/system_bd.tcl 2017-02-16 14:56:25 +02:00
fmcadc4 hdlmake.pl- updates 2016-12-01 13:52:11 -05:00
fmcadc5 fmcadc5: Updated default parameters 2017-02-20 17:13:58 +02:00
fmcjesdadc1 fmcjesdadc1: Update xcvr configuration to the default one used for this board 2017-04-12 14:41:43 +03:00
fmcomms2 fmcomms2/zc706pr- prcfg is a single clock synchronous design 2017-02-06 10:59:18 -05:00
fmcomms5 zcu102/*- actual clock == desired clock 2017-02-06 12:53:47 -05:00
fmcomms7 fmcomms7/zc706: Disabele axi_spi constraint file 2016-12-13 19:18:18 +02:00
fmcomms11 projects/- xcvr updates 2016-11-22 16:23:05 -05:00
imageon imageon: Invert HDMI TX clock 2016-11-29 15:43:24 +01:00
m2k m2k: standalone, added explicit fclk_clk0 and fclk_clk1 constraints 2017-02-13 12:02:59 +02:00
motcon2_fmc motcon_fmc: Tie unused pins to GND 2016-12-13 19:20:13 +02:00
pluto pluto: Interpolation, connect fifo_rd_valid to s_axis_data_tvalid 2017-02-13 18:08:52 +02:00
pzsdr1 pzsdr1: ccbox, moved I2S core to DMA0 and DMA1 to fix critical warnings 2017-02-14 14:51:49 +02:00
pzsdr2 pzsdr2: ccusb, renamed clk_out to clkout_in 2017-02-14 11:58:11 +02:00
scripts scripts: fixed tcl syntax for altera projects not meeting timing 2017-02-16 21:21:51 +02:00
usb_fx3 updated makefiles 2016-12-09 23:06:41 +02:00
usdrx1 Make: Update Makefiles 2017-02-10 16:32:58 +02:00
usrpe31x usrpe31x: Fix Makefile 2016-12-06 11:07:42 +02:00
Makefile Make: Update Makefiles 2017-02-10 16:32:58 +02:00