281 lines
9.3 KiB
Verilog
281 lines
9.3 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module avl_dacfifo #(
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parameter DAC_DATA_WIDTH = 64,
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parameter DMA_DATA_WIDTH = 64,
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parameter AVL_DATA_WIDTH = 512,
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parameter AVL_ADDRESS_WIDTH = 25,
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parameter AVL_BASE_ADDRESS = 32'h00000000,
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parameter AVL_ADDRESS_LIMIT = 32'h1fffffff) (
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// dma interface
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input dma_clk,
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input dma_rst,
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input dma_valid,
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input [(DMA_DATA_WIDTH-1):0] dma_data,
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output reg dma_ready,
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input dma_xfer_req,
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input dma_xfer_last,
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// dac interface
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input dac_clk,
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input dac_rst,
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input dac_valid,
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output reg [(DAC_DATA_WIDTH-1):0] dac_data,
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output reg dac_dunf,
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output dac_xfer_out,
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input bypass,
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// avalon interface
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input avl_clk,
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input avl_reset,
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output reg [(AVL_ADDRESS_WIDTH-1):0] avl_address,
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output reg [ 6:0] avl_burstcount,
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output reg [ 63:0] avl_byteenable,
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output reg avl_read,
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input [(AVL_DATA_WIDTH-1):0] avl_readdata,
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input avl_readdata_valid,
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input avl_ready,
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output reg avl_write,
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output reg [(AVL_DATA_WIDTH-1):0] avl_writedata);
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localparam FIFO_BYPASS = (DAC_DATA_WIDTH == DMA_DATA_WIDTH) ? 1 : 0;
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// internal register
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reg dma_bypass_m1 = 1'b0;
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reg dma_bypass = 1'b0;
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reg dac_bypass_m1 = 1'b0;
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reg dac_bypass = 1'b0;
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reg dac_xfer_out_m1 = 1'b0;
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reg dac_xfer_out_int = 1'b0;
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reg dac_xfer_out_bypass = 1'b0;
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reg avl_xfer_wren = 1'b0;
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reg avl_dma_xfer_req = 1'b0;
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reg avl_dma_xfer_req_m1 = 1'b0;
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// internal signals
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wire dma_ready_wr_s;
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wire avl_read_s;
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wire avl_write_s;
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wire [(AVL_DATA_WIDTH-1):0] avl_writedata_s;
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wire [ 24:0] avl_wr_address_s;
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wire [ 24:0] avl_rd_address_s;
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wire [ 24:0] avl_last_address_s;
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wire [ 63:0] avl_last_byteenable_s;
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wire [ 5:0] avl_wr_burstcount_s;
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wire [ 5:0] avl_rd_burstcount_s;
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wire [ 63:0] avl_wr_byteenable_s;
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wire [ 63:0] avl_rd_byteenable_s;
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wire avl_xfer_out_s;
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wire [(DAC_DATA_WIDTH-1):0] dac_data_fifo_s;
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wire [(DAC_DATA_WIDTH-1):0] dac_data_bypass_s;
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wire dac_xfer_fifo_out_s;
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wire dac_dunf_fifo_s;
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avl_dacfifo_wr #(
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.AVL_DATA_WIDTH (AVL_DATA_WIDTH),
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.DMA_DATA_WIDTH (DMA_DATA_WIDTH),
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.AVL_DDR_BASE_ADDRESS (AVL_BASE_ADDRESS),
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.DMA_MEM_ADDRESS_WIDTH(8)
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) i_wr (
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.dma_clk (dma_clk),
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.dma_data (dma_data),
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.dma_ready (dma_ready),
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.dma_ready_out (dma_ready_wr_s),
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.dma_valid (dma_valid),
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.dma_xfer_req (dma_xfer_req),
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.dma_xfer_last (dma_xfer_last),
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.dma_last_beat (),
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.avl_last_address (avl_last_address_s),
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.avl_last_byteenable (avl_last_byteenable_s),
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.avl_clk (avl_clk),
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.avl_reset (avl_reset),
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.avl_address (avl_wr_address_s),
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.avl_burstcount (avl_wr_burstcount_s),
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.avl_byteenable (avl_wr_byteenable_s),
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.avl_ready (avl_ready),
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.avl_write (avl_write_s),
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.avl_data (avl_writedata_s),
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.avl_xfer_req (avl_xfer_out_s)
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);
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avl_dacfifo_rd #(
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.AVL_DATA_WIDTH(AVL_DATA_WIDTH),
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.DAC_DATA_WIDTH(DAC_DATA_WIDTH),
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.AVL_DDR_BASE_ADDRESS(AVL_BASE_ADDRESS),
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.AVL_DDR_ADDRESS_LIMIT(AVL_ADDRESS_LIMIT),
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.DAC_MEM_ADDRESS_WIDTH(8)
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) i_rd (
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.dac_clk(dac_clk),
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.dac_reset(dac_rst),
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.dac_valid(dac_valid),
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.dac_data(dac_data_fifo_s),
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.dac_xfer_req(dac_xfer_fifo_out_s),
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.dac_dunf(dac_dunf_fifo_s),
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.avl_clk(avl_clk),
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.avl_reset(avl_reset),
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.avl_address(avl_rd_address_s),
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.avl_burstcount(avl_rd_burstcount_s),
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.avl_byteenable(avl_rd_byteenable_s),
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.avl_ready(avl_ready),
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.avl_readdatavalid(avl_readdata_valid),
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.avl_read(avl_read_s),
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.avl_data(avl_readdata),
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.avl_last_address(avl_last_address_s),
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.avl_last_byteenable(avl_last_byteenable_s),
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.avl_xfer_req(avl_xfer_out_s));
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// avalon address multiplexer and output registers
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always @(posedge avl_clk) begin
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avl_dma_xfer_req_m1 <= dma_xfer_req;
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avl_dma_xfer_req <= avl_dma_xfer_req_m1;
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end
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always @(posedge avl_clk) begin
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if (avl_reset == 1) begin
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avl_xfer_wren <= 0;
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end else begin
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if (avl_dma_xfer_req == 1) begin
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avl_xfer_wren <= 1;
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end
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if (avl_xfer_out_s == 1) begin
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avl_xfer_wren <= 0;
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end
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end
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end
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always @(posedge avl_clk) begin
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if (avl_reset == 1'b1) begin
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avl_address <= 0;
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avl_burstcount <= 0;
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avl_byteenable <= 0;
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avl_read <= 0;
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avl_write <= 0;
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avl_writedata <= 0;
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end else begin
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avl_address <= (avl_xfer_wren == 1'b1) ? avl_wr_address_s : avl_rd_address_s;
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avl_burstcount <= (avl_xfer_wren == 1'b1) ? avl_wr_burstcount_s : avl_rd_burstcount_s;
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avl_byteenable <= (avl_xfer_wren == 1'b1) ? avl_wr_byteenable_s : avl_rd_byteenable_s;
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avl_read <= avl_read_s;
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avl_write <= avl_write_s;
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avl_writedata <= avl_writedata_s;
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end
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end
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// bypass logic -- supported if DAC_DATA_WIDTH == DMA_DATA_WIDTH
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generate
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if (FIFO_BYPASS) begin
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util_dacfifo_bypass #(
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.DAC_DATA_WIDTH (DAC_DATA_WIDTH),
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.DMA_DATA_WIDTH (DMA_DATA_WIDTH)
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) i_dacfifo_bypass (
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.dma_clk(dma_clk),
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.dma_data(dma_data),
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.dma_ready(dma_ready),
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.dma_ready_out(dma_ready_bypass_s),
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.dma_valid(dma_valid),
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.dma_xfer_req(dma_xfer_req),
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.dac_clk(dac_clk),
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.dac_rst(dac_rst),
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.dac_valid(dac_valid),
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.dac_data(dac_data_bypass_s),
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.dac_dunf(dac_dunf_bypass_s)
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);
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always @(posedge dma_clk) begin
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dma_bypass_m1 <= bypass;
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dma_bypass <= dma_bypass_m1;
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end
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always @(posedge dac_clk) begin
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dac_bypass_m1 <= bypass;
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dac_bypass <= dac_bypass_m1;
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dac_xfer_out_m1 <= dma_xfer_req;
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dac_xfer_out_bypass <= dac_xfer_out_m1;
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end
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// mux for the dma_ready
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always @(posedge dma_clk) begin
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dma_ready <= (dma_bypass) ? dma_ready_bypass_s : dma_ready_wr_s;
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end
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// mux for dac data
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always @(posedge dac_clk) begin
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if (dac_valid) begin
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dac_data <= (dac_bypass) ? dac_data_bypass_s : dac_data_fifo_s;
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end
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dac_xfer_out_int <= (dac_bypass) ? dac_xfer_out_bypass : dac_xfer_fifo_out_s;
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dac_dunf <= (dac_bypass) ? dac_dunf_bypass_s : dac_dunf_fifo_s;
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end
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end else begin /* if (~FIFO_BYPASS) */
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always @(posedge dma_clk) begin
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dma_ready <= dma_ready_wr_s;
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end
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always @(posedge dac_clk) begin
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if (dac_valid) begin
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dac_data <= dac_data_fifo_s;
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end
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dac_xfer_out_int <= dac_xfer_fifo_out_s;
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dac_dunf <= dac_dunf_fifo_s;
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end
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end
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endgenerate
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// the ad_mem_asym memory read interface has a 3 clock cycle delay, from the
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// moment of the address change until a valid data arrives on the bus;
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// because the dac_xfer_out is going to validate the outgoing samples (in conjunction
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// with the DAC VALID, which is free a running signal), this module will compensate
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// this delay, to prevent duplicated samples in the beginning of the
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// transaction
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util_delay #(
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.DATA_WIDTH(1),
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.DELAY_CYCLES(3)
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) i_delay (
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.clk(dac_clk),
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.reset(dac_reset),
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.din(dac_xfer_out_int),
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.dout(dac_xfer_out));
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endmodule
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