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pluto_hdl_adi/library/common
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Matthew Fornero b99117e686 up_axi: Same cycle BVALID/READY fails on Altera 
The Qsys interconnect does not handle the assertion of BVALID on the
same cycle as [A]WREADY. Add a single cycle of delay to prevent
deadlocks.

Similar to:
2817ccdb22
("up_axi: altera can not handle same clock assertion of arready and rvalid")

Signed-off-by: Matthew Fornero <matt.fornero@mathworks.com>
 		2016-08-01 12:17:10 +03:00
..
altera ad_*_in: register post-iob 2016-05-16 12:19:38 -04:00
ad_addsub.v hdl/library: Update the IP parameters 2015-08-19 14:11:47 +03:00
ad_axi_ip_constr.sdc dac/adc- make common instances 2015-08-21 14:41:09 -04:00
ad_axi_ip_constr.xdc ip-constr- register name changes 2015-08-27 11:18:00 -04:00
ad_axis_inf_rx.v Add .gitattributes file 2015-06-26 11:07:10 +02:00
ad_cmos_clk.v library/common- altera variations 2016-05-04 13:42:11 -04:00
ad_cmos_in.v ad9361- cmos mode initial commit 2016-03-04 10:39:48 -05:00
ad_cmos_out.v ad9361- cmos mode initial commit 2016-03-04 10:39:48 -05:00
ad_csc_1.v Add .gitattributes file 2015-06-26 11:07:10 +02:00
ad_csc_1_add.v Add .gitattributes file 2015-06-26 11:07:10 +02:00
ad_csc_1_mul.v library: Fixed changes related to parameters 2015-08-20 18:13:54 +03:00
ad_csc_CrYCb2RGB.v imageon_zc706: Updates and fixes 2015-03-27 18:57:32 +02:00
ad_csc_RGB2CrYCb.v Add .gitattributes file 2015-06-26 11:07:10 +02:00
ad_datafmt.v Add .gitattributes file 2015-06-26 11:07:10 +02:00
ad_dcfilter.v common library: Registered dc_filter and iq_correction coefficients 2015-09-16 14:24:18 +03:00
ad_dds.v ad_dds: Registered dds_scale so that Vivado can optimally map the dsp block 2015-10-09 13:43:14 +03:00
ad_dds_1.v Add .gitattributes file 2015-06-26 11:07:10 +02:00
ad_dds_sine.v Add .gitattributes file 2015-06-26 11:07:10 +02:00
ad_edge_detect.v ad_edge_detect: Add a flop to output, reset is active high 2015-12-14 15:40:29 +02:00
ad_gt_channel.v hdl/library: Update the IP parameters 2015-08-19 14:11:47 +03:00
ad_gt_channel_1.v up_gt: separate pll resets to tx/rx 2015-10-02 13:58:30 -04:00
ad_gt_common.v hdl/library: Update the IP parameters 2015-08-19 14:11:47 +03:00
ad_gt_common_1.v up_gt_channel: Move the VERSION register to up_gt_channel, in order to preserve its address 2015-09-29 14:19:52 +03:00
ad_gt_es.v hdl/library: Update the IP parameters 2015-08-19 14:11:47 +03:00
ad_gt_es_axi.v axi_jesd_gt- per lane split-up 2015-08-13 13:03:51 -04:00
ad_iobuf.v Add .gitattributes file 2015-06-26 11:07:10 +02:00
ad_iqcor.v common library: Registered dc_filter and iq_correction coefficients 2015-09-16 14:24:18 +03:00
ad_jesd_align.v jesd-align-- xilinx/altera merge 2015-07-21 10:57:00 -04:00
ad_lvds_clk.v ad_lvds_clk: Fixed assignment mismatched 2016-05-09 10:32:18 +03:00
ad_lvds_in.v ad_lvds* - updates 2016-03-04 10:39:48 -05:00
ad_lvds_out.v common/ad_lvds_out- add single ended 2015-08-27 11:41:47 -04:00
ad_mem.v hdl/library: Update the IP parameters 2015-08-19 14:11:47 +03:00
ad_mem_asym.v ad_mem_asym: Add support for more ratios. 2016-04-19 11:18:30 +03:00
ad_mmcm_drp.v common/mmcm: add another clock 2016-03-22 12:50:59 -04:00
ad_mul.v library: Fixed changes related to parameters 2015-08-20 18:13:54 +03:00
ad_pnmon.v Add .gitattributes file 2015-06-26 11:07:10 +02:00
ad_rst.v library: ad_rst, added comment so that the registers are not minimized away 2015-11-24 10:33:38 +02:00
ad_serdes_clk.v common/mmcm: add another clock 2016-03-22 12:50:59 -04:00
ad_serdes_in.v library: Fixed changes related to parameters 2015-08-20 18:13:54 +03:00
ad_serdes_out.v library: Fixed changes related to parameters 2015-08-20 18:13:54 +03:00
ad_ss_422to444.v hdl/library: Update the IP parameters 2015-08-19 14:11:47 +03:00
ad_ss_444to422.v hdl/library: Update the IP parameters 2015-08-19 14:11:47 +03:00
ad_tdd_control.v ad_tdd_control: Add an on/off switch to the receive datapath 2016-08-01 11:49:27 +03:00
ad_xcvr_rx_if.v library/common- xcvr interface logic 2016-07-21 16:09:33 -04:00
axi_ctrlif.vhd Add .gitattributes file 2015-06-26 11:07:10 +02:00
axi_streaming_dma_rx_fifo.vhd Add .gitattributes file 2015-06-26 11:07:10 +02:00
axi_streaming_dma_tx_fifo.vhd Add .gitattributes file 2015-06-26 11:07:10 +02:00
dma_fifo.vhd Add .gitattributes file 2015-06-26 11:07:10 +02:00
pl330_dma_fifo.vhd Add .gitattributes file 2015-06-26 11:07:10 +02:00
sync_bits.v hdl/library: Update the IP parameters 2015-08-19 14:11:47 +03:00
sync_gray.v hdl/library: Update the IP parameters 2015-08-19 14:11:47 +03:00
up_adc_channel.v adc/dac - prefix parameters 2016-02-17 14:16:04 -05:00
up_adc_common.v adc/dac - prefix parameters 2016-02-17 14:16:04 -05:00
up_axi.v up_axi: Same cycle BVALID/READY fails on Altera 2016-08-01 12:17:10 +03:00
up_clkgen.v library: Axi_clkgen, added register for controlling the source clock. 2015-11-25 11:16:32 +02:00
up_clock_mon.v common/up_- change to asynchronous resets 2015-08-13 13:03:51 -04:00
up_dac_channel.v up-dac- support iq mode 2016-07-21 11:58:03 -04:00
up_dac_common.v up_dac_common- typo- unf register reset 2016-07-28 13:44:57 -04:00
up_delay_cntrl.v up_delay_cntrl- cosmetics 2015-08-28 13:16:18 -04:00
up_gt.v up_gt_channel: Move the VERSION register to up_gt_channel, in order to preserve its address 2015-09-29 14:19:52 +03:00
up_gt_channel.v library/common- reset fix 2015-10-23 14:32:35 -04:00
up_hdmi_rx.v axi_hdmi_rx: Update constraint file and fix reset line 2015-09-29 18:49:30 +03:00
up_hdmi_tx.v up_hdmi_tx: Fixed data path width 2016-06-14 14:27:03 +03:00
up_pmod.v hdl/library: Update the IP parameters 2015-08-19 14:11:47 +03:00
up_tdd_cntrl.v ad_tdd_control: Add an on/off switch to the receive datapath 2016-08-01 11:49:27 +03:00
up_xcvr.v hdl/library: Update the IP parameters 2015-08-19 14:11:47 +03:00
up_xfer_cntrl.v common/up_- change to asynchronous resets 2015-08-13 13:03:51 -04:00
up_xfer_status.v common/up_- change to asynchronous resets 2015-08-13 13:03:51 -04:00
util_pulse_gen.v common/util_pulse_gen: Rename the ad_tdd_sync module 2016-06-09 10:07:47 +03:00