221 lines
7.2 KiB
Verilog
221 lines
7.2 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ps
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module ad_gt_common_1 (
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// reset and clocks
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qpll0_rst,
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qpll0_ref_clk_in,
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qpll1_rst,
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qpll1_ref_clk_in,
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qpll_clk,
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qpll_ref_clk,
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qpll_locked,
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// bus interface
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up_rstn,
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up_clk,
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up_wreq,
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up_waddr,
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up_wdata,
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up_wack,
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up_rreq,
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up_raddr,
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up_rdata,
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up_rack);
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// parameters
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parameter integer ID = 0;
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parameter integer GTH_OR_GTX_N = 0;
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parameter integer QPLL0_ENABLE = 1;
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parameter integer QPLL0_REFCLK_DIV = 2;
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parameter [26:0] QPLL0_CFG = 27'h06801C1;
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parameter integer QPLL0_FBDIV_RATIO = 1'b1;
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parameter [ 9:0] QPLL0_FBDIV = 10'b0000110000;
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parameter integer QPLL1_ENABLE = 1;
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parameter integer QPLL1_REFCLK_DIV = 2;
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parameter [26:0] QPLL1_CFG = 27'h06801C1;
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parameter integer QPLL1_FBDIV_RATIO = 1'b1;
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parameter [ 9:0] QPLL1_FBDIV = 10'b0000110000;
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// reset and clocks
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input qpll0_rst;
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input qpll0_ref_clk_in;
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input qpll1_rst;
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input qpll1_ref_clk_in;
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output [ 7:0] qpll_clk;
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output [ 7:0] qpll_ref_clk;
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output [ 7:0] qpll_locked;
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// bus interface
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input up_rstn;
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input up_clk;
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input up_wreq;
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input [13:0] up_waddr;
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input [31:0] up_wdata;
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output up_wack;
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input up_rreq;
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input [13:0] up_raddr;
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output [31:0] up_rdata;
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output up_rack;
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// internal signals
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wire up_drp_qpll0_sel_s;
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wire up_drp_qpll0_wr_s;
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wire [11:0] up_drp_qpll0_addr_s;
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wire [15:0] up_drp_qpll0_wdata_s;
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wire [15:0] up_drp_qpll0_rdata_s;
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wire up_drp_qpll0_ready_s;
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wire up_drp_qpll1_sel_s;
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wire up_drp_qpll1_wr_s;
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wire [11:0] up_drp_qpll1_addr_s;
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wire [15:0] up_drp_qpll1_wdata_s;
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wire [15:0] up_drp_qpll1_rdata_s;
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wire up_drp_qpll1_ready_s;
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// replicate to match channels
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assign qpll_clk[1] = qpll_clk[0];
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assign qpll_ref_clk[1] = qpll_ref_clk[0];
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assign qpll_locked[1] = qpll_locked[0];
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assign qpll_clk[2] = qpll_clk[0];
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assign qpll_ref_clk[2] = qpll_ref_clk[0];
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assign qpll_locked[2] = qpll_locked[0];
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assign qpll_clk[3] = qpll_clk[0];
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assign qpll_ref_clk[3] = qpll_ref_clk[0];
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assign qpll_locked[3] = qpll_locked[0];
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assign qpll_clk[5] = qpll_clk[4];
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assign qpll_ref_clk[5] = qpll_ref_clk[4];
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assign qpll_locked[5] = qpll_locked[4];
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assign qpll_clk[6] = qpll_clk[4];
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assign qpll_ref_clk[6] = qpll_ref_clk[4];
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assign qpll_locked[6] = qpll_locked[4];
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assign qpll_clk[7] = qpll_clk[4];
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assign qpll_ref_clk[7] = qpll_ref_clk[4];
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assign qpll_locked[7] = qpll_locked[4];
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// instantiations
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ad_gt_common #(
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.GTH_OR_GTX_N (GTH_OR_GTX_N),
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.QPLL_ENABLE (QPLL0_ENABLE),
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.QPLL_REFCLK_DIV (QPLL0_REFCLK_DIV),
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.QPLL_CFG (QPLL0_CFG),
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.QPLL_FBDIV_RATIO (QPLL0_FBDIV_RATIO),
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.QPLL_FBDIV (QPLL0_FBDIV))
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i_qpll_0 (
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.qpll_ref_clk_in (qpll0_ref_clk_in),
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.qpll_rst (qpll0_rst),
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.qpll_clk (qpll_clk[0]),
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.qpll_ref_clk (qpll_ref_clk[0]),
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.qpll_locked (qpll_locked[0]),
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.up_clk (up_clk),
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.up_drp_sel (up_drp_qpll0_sel_s),
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.up_drp_addr (up_drp_qpll0_addr_s),
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.up_drp_wr (up_drp_qpll0_wr_s),
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.up_drp_wdata (up_drp_qpll0_wdata_s),
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.up_drp_rdata (up_drp_qpll0_rdata_s),
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.up_drp_ready (up_drp_qpll0_ready_s));
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ad_gt_common #(
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.GTH_OR_GTX_N (GTH_OR_GTX_N),
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.QPLL_ENABLE (QPLL1_ENABLE),
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.QPLL_REFCLK_DIV (QPLL1_REFCLK_DIV),
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.QPLL_CFG (QPLL1_CFG),
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.QPLL_FBDIV_RATIO (QPLL1_FBDIV_RATIO),
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.QPLL_FBDIV (QPLL1_FBDIV))
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i_qpll_1 (
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.qpll_ref_clk_in (qpll1_ref_clk_in),
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.qpll_rst (qpll1_rst),
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.qpll_clk (qpll_clk[4]),
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.qpll_ref_clk (qpll_ref_clk[4]),
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.qpll_locked (qpll_locked[4]),
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.up_clk (up_clk),
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.up_drp_sel (up_drp_qpll1_sel_s),
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.up_drp_addr (up_drp_qpll1_addr_s),
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.up_drp_wr (up_drp_qpll1_wr_s),
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.up_drp_wdata (up_drp_qpll1_wdata_s),
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.up_drp_rdata (up_drp_qpll1_rdata_s),
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.up_drp_ready (up_drp_qpll1_ready_s));
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up_gt #(
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.GTH_OR_GTX_N (GTH_OR_GTX_N))
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i_up (
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.up_drp_qpll0_sel (up_drp_qpll0_sel_s),
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.up_drp_qpll0_wr (up_drp_qpll0_wr_s),
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.up_drp_qpll0_addr (up_drp_qpll0_addr_s),
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.up_drp_qpll0_wdata (up_drp_qpll0_wdata_s),
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.up_drp_qpll0_rdata (up_drp_qpll0_rdata_s),
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.up_drp_qpll0_ready (up_drp_qpll0_ready_s),
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.up_drp_qpll1_sel (up_drp_qpll1_sel_s),
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.up_drp_qpll1_wr (up_drp_qpll1_wr_s),
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.up_drp_qpll1_addr (up_drp_qpll1_addr_s),
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.up_drp_qpll1_wdata (up_drp_qpll1_wdata_s),
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.up_drp_qpll1_rdata (up_drp_qpll1_rdata_s),
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.up_drp_qpll1_ready (up_drp_qpll1_ready_s),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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