458 lines
14 KiB
Verilog
458 lines
14 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module ad_gt_es_axi (
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// es interface
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up_rstn,
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up_clk,
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up_es_dma_req_0,
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up_es_dma_addr_0,
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up_es_dma_data_0,
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up_es_dma_ack_0,
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up_es_dma_err_0,
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up_es_dma_req_1,
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up_es_dma_addr_1,
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up_es_dma_data_1,
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up_es_dma_ack_1,
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up_es_dma_err_1,
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up_es_dma_req_2,
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up_es_dma_addr_2,
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up_es_dma_data_2,
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up_es_dma_ack_2,
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up_es_dma_err_2,
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up_es_dma_req_3,
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up_es_dma_addr_3,
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up_es_dma_data_3,
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up_es_dma_ack_3,
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up_es_dma_err_3,
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up_es_dma_req_4,
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up_es_dma_addr_4,
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up_es_dma_data_4,
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up_es_dma_ack_4,
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up_es_dma_err_4,
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up_es_dma_req_5,
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up_es_dma_addr_5,
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up_es_dma_data_5,
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up_es_dma_ack_5,
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up_es_dma_err_5,
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up_es_dma_req_6,
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up_es_dma_addr_6,
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up_es_dma_data_6,
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up_es_dma_ack_6,
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up_es_dma_err_6,
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up_es_dma_req_7,
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up_es_dma_addr_7,
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up_es_dma_data_7,
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up_es_dma_ack_7,
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up_es_dma_err_7,
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// axi4 interface
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axi_awvalid,
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axi_awaddr,
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axi_awprot,
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axi_awready,
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axi_wvalid,
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axi_wdata,
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axi_wstrb,
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axi_wready,
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axi_bvalid,
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axi_bresp,
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axi_bready,
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axi_arvalid,
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axi_araddr,
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axi_arprot,
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axi_arready,
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axi_rvalid,
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axi_rresp,
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axi_rdata,
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axi_rready);
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// state machine (fair RR?)
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localparam [ 3:0] AXI_FSM_SCAN_0 = 4'h0;
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localparam [ 3:0] AXI_FSM_SCAN_1 = 4'h1;
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localparam [ 3:0] AXI_FSM_SCAN_2 = 4'h2;
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localparam [ 3:0] AXI_FSM_SCAN_3 = 4'h3;
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localparam [ 3:0] AXI_FSM_SCAN_4 = 4'h4;
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localparam [ 3:0] AXI_FSM_SCAN_5 = 4'h5;
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localparam [ 3:0] AXI_FSM_SCAN_6 = 4'h6;
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localparam [ 3:0] AXI_FSM_SCAN_7 = 4'h7;
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localparam [ 3:0] AXI_FSM_WRITE = 4'h8;
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localparam [ 3:0] AXI_FSM_WAIT = 4'h9;
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localparam [ 3:0] AXI_FSM_ACK = 4'ha;
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// es interface
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input up_rstn;
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input up_clk;
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input up_es_dma_req_0;
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input [31:0] up_es_dma_addr_0;
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input [31:0] up_es_dma_data_0;
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output up_es_dma_ack_0;
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output up_es_dma_err_0;
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input up_es_dma_req_1;
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input [31:0] up_es_dma_addr_1;
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input [31:0] up_es_dma_data_1;
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output up_es_dma_ack_1;
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output up_es_dma_err_1;
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input up_es_dma_req_2;
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input [31:0] up_es_dma_addr_2;
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input [31:0] up_es_dma_data_2;
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output up_es_dma_ack_2;
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output up_es_dma_err_2;
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input up_es_dma_req_3;
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input [31:0] up_es_dma_addr_3;
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input [31:0] up_es_dma_data_3;
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output up_es_dma_ack_3;
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output up_es_dma_err_3;
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input up_es_dma_req_4;
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input [31:0] up_es_dma_addr_4;
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input [31:0] up_es_dma_data_4;
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output up_es_dma_ack_4;
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output up_es_dma_err_4;
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input up_es_dma_req_5;
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input [31:0] up_es_dma_addr_5;
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input [31:0] up_es_dma_data_5;
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output up_es_dma_ack_5;
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output up_es_dma_err_5;
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input up_es_dma_req_6;
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input [31:0] up_es_dma_addr_6;
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input [31:0] up_es_dma_data_6;
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output up_es_dma_ack_6;
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output up_es_dma_err_6;
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input up_es_dma_req_7;
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input [31:0] up_es_dma_addr_7;
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input [31:0] up_es_dma_data_7;
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output up_es_dma_ack_7;
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output up_es_dma_err_7;
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// axi4 interface
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output axi_awvalid;
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output [31:0] axi_awaddr;
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output [ 2:0] axi_awprot;
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input axi_awready;
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output axi_wvalid;
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output [31:0] axi_wdata;
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output [ 3:0] axi_wstrb;
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input axi_wready;
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input axi_bvalid;
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input [ 1:0] axi_bresp;
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output axi_bready;
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output axi_arvalid;
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output [31:0] axi_araddr;
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output [ 2:0] axi_arprot;
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input axi_arready;
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input axi_rvalid;
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input [31:0] axi_rdata;
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input [ 1:0] axi_rresp;
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output axi_rready;
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// internal registers
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reg up_es_dma_ack_0 = 'd0;
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reg up_es_dma_err_0 = 'd0;
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reg up_es_dma_ack_1 = 'd0;
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reg up_es_dma_err_1 = 'd0;
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reg up_es_dma_ack_2 = 'd0;
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reg up_es_dma_err_2 = 'd0;
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reg up_es_dma_ack_3 = 'd0;
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reg up_es_dma_err_3 = 'd0;
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reg up_es_dma_ack_4 = 'd0;
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reg up_es_dma_err_4 = 'd0;
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reg up_es_dma_ack_5 = 'd0;
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reg up_es_dma_err_5 = 'd0;
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reg up_es_dma_ack_6 = 'd0;
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reg up_es_dma_err_6 = 'd0;
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reg up_es_dma_ack_7 = 'd0;
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reg up_es_dma_err_7 = 'd0;
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reg axi_awvalid = 'd0;
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reg [31:0] axi_awaddr = 'd0;
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reg axi_wvalid = 'd0;
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reg [31:0] axi_wdata = 'd0;
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reg axi_error = 'd0;
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reg [ 2:0] axi_sel = 'd0;
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reg [ 3:0] axi_fsm = 'd0;
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// axi write interface
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assign axi_awprot = 3'd0;
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assign axi_wstrb = 4'hf;
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assign axi_bready = 1'd1;
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assign axi_arvalid = 1'd0;
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assign axi_araddr = 32'd0;
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assign axi_arprot = 3'd0;
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assign axi_rready = 1'd1;
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_es_dma_ack_0 <= 1'b0;
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up_es_dma_err_0 <= 1'b0;
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up_es_dma_ack_1 <= 1'b0;
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up_es_dma_err_1 <= 1'b0;
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up_es_dma_ack_2 <= 1'b0;
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up_es_dma_err_2 <= 1'b0;
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up_es_dma_ack_3 <= 1'b0;
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up_es_dma_err_3 <= 1'b0;
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up_es_dma_ack_4 <= 1'b0;
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up_es_dma_err_4 <= 1'b0;
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up_es_dma_ack_5 <= 1'b0;
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up_es_dma_err_5 <= 1'b0;
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up_es_dma_ack_6 <= 1'b0;
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up_es_dma_err_6 <= 1'b0;
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up_es_dma_ack_7 <= 1'b0;
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up_es_dma_err_7 <= 1'b0;
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end else begin
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if ((axi_fsm == AXI_FSM_ACK) && (axi_sel == 3'd0)) begin
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up_es_dma_ack_0 <= 1'b1;
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up_es_dma_err_0 <= axi_error;
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end else begin
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up_es_dma_ack_0 <= 1'b0;
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up_es_dma_err_0 <= 1'b0;
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end
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if ((axi_fsm == AXI_FSM_ACK) && (axi_sel == 3'd1)) begin
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up_es_dma_ack_1 <= 1'b1;
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up_es_dma_err_1 <= axi_error;
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end else begin
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up_es_dma_ack_1 <= 1'b0;
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up_es_dma_err_1 <= 1'b0;
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end
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if ((axi_fsm == AXI_FSM_ACK) && (axi_sel == 3'd2)) begin
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up_es_dma_ack_2 <= 1'b1;
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up_es_dma_err_2 <= axi_error;
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end else begin
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up_es_dma_ack_2 <= 1'b0;
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up_es_dma_err_2 <= 1'b0;
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end
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if ((axi_fsm == AXI_FSM_ACK) && (axi_sel == 3'd3)) begin
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up_es_dma_ack_3 <= 1'b1;
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up_es_dma_err_3 <= axi_error;
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end else begin
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up_es_dma_ack_3 <= 1'b0;
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up_es_dma_err_3 <= 1'b0;
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end
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if ((axi_fsm == AXI_FSM_ACK) && (axi_sel == 3'd4)) begin
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up_es_dma_ack_4 <= 1'b1;
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up_es_dma_err_4 <= axi_error;
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end else begin
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up_es_dma_ack_4 <= 1'b0;
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up_es_dma_err_4 <= 1'b0;
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end
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if ((axi_fsm == AXI_FSM_ACK) && (axi_sel == 3'd5)) begin
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up_es_dma_ack_5 <= 1'b1;
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up_es_dma_err_5 <= axi_error;
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end else begin
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up_es_dma_ack_5 <= 1'b0;
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up_es_dma_err_5 <= 1'b0;
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end
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if ((axi_fsm == AXI_FSM_ACK) && (axi_sel == 3'd6)) begin
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up_es_dma_ack_6 <= 1'b1;
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up_es_dma_err_6 <= axi_error;
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end else begin
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up_es_dma_ack_6 <= 1'b0;
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up_es_dma_err_6 <= 1'b0;
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end
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if ((axi_fsm == AXI_FSM_ACK) && (axi_sel == 3'd7)) begin
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up_es_dma_ack_7 <= 1'b1;
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up_es_dma_err_7 <= axi_error;
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end else begin
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up_es_dma_ack_7 <= 1'b0;
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up_es_dma_err_7 <= 1'b0;
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end
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end
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end
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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axi_awvalid <= 'b0;
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axi_awaddr <= 'd0;
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axi_wvalid <= 'b0;
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axi_wdata <= 'd0;
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axi_error <= 'd0;
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end else begin
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if ((axi_awvalid == 1'b1) && (axi_awready == 1'b1)) begin
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axi_awvalid <= 1'b0;
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axi_awaddr <= 32'd0;
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end else if (axi_fsm == AXI_FSM_WRITE) begin
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axi_awvalid <= 1'b1;
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case (axi_sel)
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3'b000: axi_awaddr <= up_es_dma_addr_0;
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3'b001: axi_awaddr <= up_es_dma_addr_1;
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3'b010: axi_awaddr <= up_es_dma_addr_2;
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3'b011: axi_awaddr <= up_es_dma_addr_3;
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3'b100: axi_awaddr <= up_es_dma_addr_4;
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3'b101: axi_awaddr <= up_es_dma_addr_5;
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3'b110: axi_awaddr <= up_es_dma_addr_6;
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default: axi_awaddr <= up_es_dma_addr_7;
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endcase
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end
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if ((axi_wvalid == 1'b1) && (axi_wready == 1'b1)) begin
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axi_wvalid <= 1'b0;
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axi_wdata <= 32'd0;
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end else if (axi_fsm == AXI_FSM_WRITE) begin
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axi_wvalid <= 1'b1;
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case (axi_sel)
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3'b000: axi_wdata <= up_es_dma_data_0;
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3'b001: axi_wdata <= up_es_dma_data_1;
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3'b010: axi_wdata <= up_es_dma_data_2;
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3'b011: axi_wdata <= up_es_dma_data_3;
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3'b100: axi_wdata <= up_es_dma_data_4;
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3'b101: axi_wdata <= up_es_dma_data_5;
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3'b110: axi_wdata <= up_es_dma_data_6;
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default: axi_wdata <= up_es_dma_data_7;
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endcase
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end
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if (axi_bvalid == 1'b1) begin
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axi_error <= axi_bresp[1] | axi_bresp[0];
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end
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end
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end
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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axi_sel <= 3'd0;
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axi_fsm <= AXI_FSM_SCAN_0;
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end else begin
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case (axi_fsm)
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AXI_FSM_SCAN_0: begin
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axi_sel <= 3'd0;
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if (up_es_dma_req_0 == 1'b1) begin
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axi_fsm <= AXI_FSM_WRITE;
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end else begin
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axi_fsm <= AXI_FSM_SCAN_1;
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end
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end
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AXI_FSM_SCAN_1: begin
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axi_sel <= 3'd1;
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if (up_es_dma_req_1 == 1'b1) begin
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axi_fsm <= AXI_FSM_WRITE;
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end else begin
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axi_fsm <= AXI_FSM_SCAN_2;
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end
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end
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AXI_FSM_SCAN_2: begin
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axi_sel <= 3'd2;
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if (up_es_dma_req_2 == 1'b1) begin
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axi_fsm <= AXI_FSM_WRITE;
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end else begin
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axi_fsm <= AXI_FSM_SCAN_3;
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end
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end
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AXI_FSM_SCAN_3: begin
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axi_sel <= 3'd3;
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if (up_es_dma_req_3 == 1'b1) begin
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axi_fsm <= AXI_FSM_WRITE;
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end else begin
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axi_fsm <= AXI_FSM_SCAN_4;
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end
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end
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AXI_FSM_SCAN_4: begin
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axi_sel <= 3'd4;
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if (up_es_dma_req_4 == 1'b1) begin
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axi_fsm <= AXI_FSM_WRITE;
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end else begin
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axi_fsm <= AXI_FSM_SCAN_5;
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end
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end
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AXI_FSM_SCAN_5: begin
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axi_sel <= 3'd5;
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if (up_es_dma_req_5 == 1'b1) begin
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axi_fsm <= AXI_FSM_WRITE;
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end else begin
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axi_fsm <= AXI_FSM_SCAN_6;
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end
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end
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AXI_FSM_SCAN_6: begin
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axi_sel <= 3'd6;
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if (up_es_dma_req_6 == 1'b1) begin
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axi_fsm <= AXI_FSM_WRITE;
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end else begin
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axi_fsm <= AXI_FSM_SCAN_7;
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end
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end
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AXI_FSM_SCAN_7: begin
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axi_sel <= 3'd7;
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if (up_es_dma_req_7 == 1'b1) begin
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axi_fsm <= AXI_FSM_WRITE;
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end else begin
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axi_fsm <= AXI_FSM_SCAN_0;
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end
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end
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AXI_FSM_WRITE: begin
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axi_sel <= axi_sel;
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axi_fsm <= AXI_FSM_WAIT;
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end
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AXI_FSM_WAIT: begin
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axi_sel <= axi_sel;
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if (axi_bvalid == 1'b1) begin
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axi_fsm <= AXI_FSM_ACK;
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end else begin
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axi_fsm <= AXI_FSM_WAIT;
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end
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end
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AXI_FSM_ACK: begin
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axi_sel <= axi_sel;
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case (axi_sel)
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3'b000: axi_fsm <= AXI_FSM_SCAN_1;
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3'b001: axi_fsm <= AXI_FSM_SCAN_2;
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3'b010: axi_fsm <= AXI_FSM_SCAN_3;
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3'b011: axi_fsm <= AXI_FSM_SCAN_4;
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3'b100: axi_fsm <= AXI_FSM_SCAN_5;
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3'b101: axi_fsm <= AXI_FSM_SCAN_6;
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3'b110: axi_fsm <= AXI_FSM_SCAN_7;
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default: axi_fsm <= AXI_FSM_SCAN_0;
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endcase
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end
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default: begin
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axi_fsm <= AXI_FSM_SCAN_0;
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end
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endcase
|
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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