84 lines
3.2 KiB
Verilog
84 lines
3.2 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// replacing Xilinx's macro with Altera's LPM
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`timescale 1ps/1ps
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module MULT_MACRO (
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CE,
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RST,
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CLK,
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A,
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B,
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P);
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parameter LATENCY = 3;
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parameter WIDTH_A = 16;
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parameter WIDTH_B = 16;
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localparam WIDTH_P = WIDTH_A + WIDTH_B;
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input CE;
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input RST;
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input CLK;
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input [WIDTH_A-1:0] A;
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input [WIDTH_B-1:0] B;
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output [WIDTH_P-1:0] P;
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lpm_mult #(
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.lpm_type ("lpm_mult"),
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.lpm_widtha (WIDTH_A),
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.lpm_widthb (WIDTH_B),
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.lpm_widthp (WIDTH_P),
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.lpm_representation ("SIGNED"),
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.lpm_pipeline (3))
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i_lpm_mult (
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.clken (CE),
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.aclr (RST),
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.sum (1'b0),
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.clock (CLK),
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.dataa (A),
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.datab (B),
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.result (P));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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