160 lines
5.2 KiB
Verilog
160 lines
5.2 KiB
Verilog
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2013(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ns
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module prcfg_dac(
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clk,
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// control ports
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control,
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status,
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// FIFO interface
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src_dac_enable,
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src_dac_data,
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src_dac_valid,
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dst_dac_enable,
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dst_dac_data,
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dst_dac_valid
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);
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parameter CHANNEL_ID = 0;
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parameter DATA_WIDTH = 16;
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localparam SYMBOL_WIDTH = 2;
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localparam RP_ID = 8'hA2;
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input clk;
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input [31:0] control;
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output [31:0] status;
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output src_dac_enable;
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input [(DATA_WIDTH-1):0] src_dac_data;
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output src_dac_valid;
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input dst_dac_enable;
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output [(DATA_WIDTH-1):0] dst_dac_data;
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input dst_dac_valid;
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// output register to improve timing
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reg [(DATA_WIDTH-1):0] dst_dac_data = 'h0;
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reg src_dac_valid = 'h0;
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reg src_dac_enable = 'h0;
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// internal registers
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reg [ 7:0] pn_data = 'hF2;
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reg [31:0] status = 'h0;
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reg [ 3:0] mode = 'h0;
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// internal wires
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wire [(SYMBOL_WIDTH-1):0] mod_data;
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wire [15:0] dac_data_fltr_i;
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wire [15:0] dac_data_fltr_q;
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// prbs function
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function [ 7:0] pn;
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input [ 7:0] din;
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reg [ 7:0] dout;
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begin
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dout[7] = din[6];
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dout[6] = din[5];
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dout[5] = din[4];
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dout[4] = din[3];
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dout[3] = din[2];
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dout[2] = din[1];
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dout[1] = din[7] ^ din[4];
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dout[0] = din[6] ^ din[3];
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pn = dout;
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end
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endfunction
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// update control and status registers
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always @(posedge clk) begin
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status <= { 24'h0, RP_ID };
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mode <= control[ 7:4];
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end
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// prbs generation
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always @(posedge clk) begin
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if((dst_dac_en == 1) && (dst_dac_enable == 1)) begin
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pn_data <= pn(pn_data);
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end
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end
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// data for the modulator (prbs or dma)
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assign mod_data = (mode == 1) ? pn_data[ 1:0] : src_dac_data[ 1:0];
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// qpsk modulator
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qpsk_mod i_qpsk_mod (
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.clk(clk),
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.data_input(mod_data),
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.data_valid(dst_dac_en),
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.data_qpsk_i(dac_data_fltr_i),
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.data_qpsk_q(dac_data_fltr_q)
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);
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// output logic
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always @(posedge clk) begin
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src_dac_enable <= dst_dac_en;
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src_dac_valid <= dst_dac_valid;
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case(mode)
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4'h0 : begin
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dst_dac_data <= src_dac_data;
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end
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4'h1 : begin
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dst_dac_data <= { dac_data_fltr_q, dac_data_fltr_i };
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end
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4'h2 : begin
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dst_dac_data <= { dac_data_fltr_q, dac_data_fltr_i };
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end
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default : begin
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end
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endcase
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end
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endmodule
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