243 lines
8.2 KiB
Verilog
243 lines
8.2 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2013 (c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ns
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module prcfg (
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clk,
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// gpio
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dac_gpio_input,
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dac_gpio_output,
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adc_gpio_input,
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adc_gpio_output,
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// tx side
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dma_dac_i0_enable,
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dma_dac_i0_data,
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dma_dac_i0_valid,
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dma_dac_q0_enable,
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dma_dac_q0_data,
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dma_dac_q0_valid,
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dma_dac_i1_enable,
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dma_dac_i1_data,
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dma_dac_i1_valid,
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dma_dac_q1_enable,
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dma_dac_q1_data,
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dma_dac_q1_valid,
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core_dac_i0_enable,
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core_dac_i0_data,
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core_dac_i0_valid,
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core_dac_q0_enable,
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core_dac_q0_data,
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core_dac_q0_valid,
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core_dac_i1_enable,
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core_dac_i1_data,
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core_dac_i1_valid,
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core_dac_q1_enable,
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core_dac_q1_data,
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core_dac_q1_valid,
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// rx side
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dma_adc_i0_enable,
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dma_adc_i0_data,
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dma_adc_i0_valid,
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dma_adc_q0_enable,
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dma_adc_q0_data,
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dma_adc_q0_valid,
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dma_adc_i1_enable,
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dma_adc_i1_data,
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dma_adc_i1_valid,
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dma_adc_q1_enable,
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dma_adc_q1_data,
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dma_adc_q1_valid,
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core_adc_i0_enable,
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core_adc_i0_data,
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core_adc_i0_valid,
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core_adc_q0_enable,
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core_adc_q0_data,
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core_adc_q0_valid,
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core_adc_i1_enable,
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core_adc_i1_data,
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core_adc_i1_valid,
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core_adc_q1_enable,
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core_adc_q1_data,
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core_adc_q1_valid);
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input clk;
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// gpio
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input [31:0] adc_gpio_input;
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output [31:0] adc_gpio_output;
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input [31:0] dac_gpio_input;
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output [31:0] dac_gpio_output;
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// tx side
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input dma_dac_i0_enable;
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output [15:0] dma_dac_i0_data;
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input dma_dac_i0_valid;
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input dma_dac_q0_enable;
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output [15:0] dma_dac_q0_data;
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input dma_dac_q0_valid;
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input dma_dac_i1_enable;
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output [15:0] dma_dac_i1_data;
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input dma_dac_i1_valid;
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input dma_dac_q1_enable;
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output [15:0] dma_dac_q1_data;
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input dma_dac_q1_valid;
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output core_dac_i0_enable;
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input [15:0] core_dac_i0_data;
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output core_dac_i0_valid;
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output core_dac_q0_enable;
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input [15:0] core_dac_q0_data;
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output core_dac_q0_valid;
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output core_dac_i1_enable;
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input [15:0] core_dac_i1_data;
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output core_dac_i1_valid;
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output core_dac_q1_enable;
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input [15:0] core_dac_q1_data;
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output core_dac_q1_valid;
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// rx side
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input dma_adc_i0_enable;
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input [15:0] dma_adc_i0_data;
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input dma_adc_i0_valid;
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input dma_adc_q0_enable;
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input [15:0] dma_adc_q0_data;
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input dma_adc_q0_valid;
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input dma_adc_i1_enable;
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input [15:0] dma_adc_i1_data;
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input dma_adc_i1_valid;
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input dma_adc_q1_enable;
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input [15:0] dma_adc_q1_data;
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input dma_adc_q1_valid;
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output core_adc_i0_enable;
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output [15:0] core_adc_i0_data;
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output core_adc_i0_valid;
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output core_adc_q0_enable;
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output [15:0] core_adc_q0_data;
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output core_adc_q0_valid;
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output core_adc_i1_enable;
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output [15:0] core_adc_i1_data;
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output core_adc_i1_valid;
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output core_adc_q1_enable;
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output [15:0] core_adc_q1_data;
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output core_adc_q1_valid;
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// fmcomms2 configuration
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localparam NUM_OF_CHANNELS = 4;
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localparam ADC_ENABLE = 1;
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localparam DAC_ENABLE = 1;
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// default top
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prcfg_top # (
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.NUM_CHANNEL (NUM_OF_CHANNELS),
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.ADC_EN (ADC_ENABLE),
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.DAC_EN (DAC_ENABLE))
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i_prcfg_top (
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.clk (clk),
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.dac_gpio_input (dac_gpio_input),
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.dac_gpio_output (dac_gpio_output),
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.adc_gpio_input (adc_gpio_input),
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.adc_gpio_output (adc_gpio_output),
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.dma_dac_0_enable (dma_dac_i0_enable),
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.dma_dac_0_data (dma_dac_i0_data),
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.dma_dac_0_valid (dma_dac_i0_valid),
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.dma_dac_1_enable (dma_dac_q0_enable),
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.dma_dac_1_data (dma_dac_q0_data),
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.dma_dac_1_valid (dma_dac_q0_valid),
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.dma_dac_2_enable (dma_dac_i1_enable),
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.dma_dac_2_data (dma_dac_i1_data),
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.dma_dac_2_valid (dma_dac_i1_valid),
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.dma_dac_3_enable (dma_dac_q1_enable),
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.dma_dac_3_data (dma_dac_q1_data),
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.dma_dac_3_valid (dma_dac_q1_valid),
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.core_dac_0_enable (core_dac_i0_enable),
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.core_dac_0_data (core_dac_i0_data),
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.core_dac_0_valid (core_dac_i0_valid),
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.core_dac_1_enable (core_dac_q0_enable),
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.core_dac_1_data (core_dac_q0_data),
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.core_dac_1_valid (core_dac_q0_valid),
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.core_dac_2_enable (core_dac_i1_enable),
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.core_dac_2_data (core_dac_i1_data),
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.core_dac_2_valid (core_dac_i1_valid),
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.core_dac_3_enable (core_dac_q1_enable),
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.core_dac_3_data (core_dac_q1_data),
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.core_dac_3_valid (core_dac_q1_valid),
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.dma_adc_0_enable (dma_adc_i0_enable),
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.dma_adc_0_data (dma_adc_i0_data),
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.dma_adc_0_valid (dma_adc_i0_valid),
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.dma_adc_1_enable (dma_adc_q0_enable),
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.dma_adc_1_data (dma_adc_q0_data),
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.dma_adc_1_valid (dma_adc_q0_valid),
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.dma_adc_2_enable (dma_adc_i1_enable),
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.dma_adc_2_data (dma_adc_i1_data),
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.dma_adc_2_valid (dma_adc_i1_valid),
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.dma_adc_3_enable (dma_adc_q1_enable),
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.dma_adc_3_data (dma_adc_q1_data),
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.dma_adc_3_valid (dma_adc_q1_valid),
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.core_adc_0_enable (core_adc_i0_enable),
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.core_adc_0_data (core_adc_i0_data),
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.core_adc_0_valid (core_adc_i0_valid),
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.core_adc_1_enable (core_adc_q0_enable),
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.core_adc_1_data (core_adc_q0_data),
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.core_adc_1_valid (core_adc_q0_valid),
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.core_adc_2_enable (core_adc_i1_enable),
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.core_adc_2_data (core_adc_i1_data),
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.core_adc_2_valid (core_adc_i1_valid),
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.core_adc_3_enable (core_adc_q1_enable),
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.core_adc_3_data (core_adc_q1_data),
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.core_adc_3_valid (core_adc_q1_valid));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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