c00a6af4db
The converters on the usdrx1 generate 2.5GB/s. This more than we can transport over the HP interconnects to the system memory. Add a dedicated DDR FIFO to design which can be used to buffer the data before it is transferred to the main memory. Also increase the interconnect clock rate from 100MHz to 200MHz and the DMA FIFO size from 4 to 8, so we can transfer the captured data faster to the main memory. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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| a5gt | ||
| common | ||
| cpld | ||
| zc706 | ||
| Makefile | ||