pluto_hdl_adi/projects/usdrx1/zc706
Lars-Peter Clausen c00a6af4db usdrx1: Add DDR FIFO
The converters on the usdrx1 generate 2.5GB/s. This more than we can
transport over the HP interconnects to the system memory.

Add a dedicated DDR FIFO to design which can be used to buffer the data
before it is transferred to the main memory.

Also increase the interconnect clock rate from 100MHz to 200MHz and the DMA
FIFO size from 4 to 8, so we can transfer the captured data faster to the
main memory.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-01 11:21:45 +02:00
..
Makefile Makefiles: Updated makefiles 2015-08-06 19:50:50 +03:00
system_bd.tcl usdrx1: Add DDR FIFO 2015-09-01 11:21:45 +02:00
system_constr.xdc Add .gitattributes file 2015-07-01 18:43:51 +02:00
system_project.tcl usdrx1: Add DDR FIFO 2015-09-01 11:21:45 +02:00
system_top.v usdrx1: Add DDR FIFO 2015-09-01 11:21:45 +02:00