118 lines
3.6 KiB
Tcl
118 lines
3.6 KiB
Tcl
# density 4GB,8GB
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proc ad_create_hbm {ip_name {density "4GB"}} {
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global hbm_sim;
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if { [info exists hbm_sim] == 0} {
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set hbm_sim 0
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}
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if {$hbm_sim == 0} {
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ad_ip_instance hbm $ip_name
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ad_ip_parameter $ip_name CONFIG.USER_HBM_DENSITY $density
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ad_ip_parameter $ip_name CONFIG.USER_APB_EN {false}
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set i_hbm_ip [get_bd_cells $ip_name]
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set num_stacks [get_property CONFIG.USER_HBM_STACK $i_hbm_ip]
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# 16 pseudo channels / sections / segments per stack
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set num_segments [expr $num_stacks*16]
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for {set i 1} {$i < $num_segments} {incr i} {
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set i_formatted [format "%02d" $i]
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ad_ip_parameter $ip_name CONFIG.USER_SAXI_${i_formatted} {false}
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}
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} else {
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# Create data storage HMB controller model (AXI slave)
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ad_ip_instance axi_vip $ip_name [list \
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INTERFACE_MODE {SLAVE} \
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]
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adi_sim_add_define "HBM_AXI=$ip_name"
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}
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}
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proc ad_create_util_hbm {name rx_tx_n src_width dst_width mem_size {axi_data_width 256} {mem_type 2}} {
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if {$mem_type == 2} {
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# HBM
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# split converter side bus into multiple AXI masters
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set number_of_masters [expr int(ceil((${rx_tx_n} == 1 ? ${dst_width}.0 : ${src_width}.0) / ${axi_data_width}.0))]
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} else {
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# DDR we have always one master
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set number_of_masters 1
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}
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ad_ip_instance util_hbm $name [list \
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LENGTH_WIDTH [log2 $mem_size] \
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SRC_DATA_WIDTH $src_width \
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DST_DATA_WIDTH $dst_width \
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AXI_DATA_WIDTH $axi_data_width \
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TX_RX_N $rx_tx_n \
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NUM_M $number_of_masters \
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MEM_TYPE $mem_type \
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]
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}
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proc ad_connect_hbm {i_hbm i_util_hbm axi_clk axi_aresetn {first_slave_index 0}} {
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global hbm_sim;
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if { [info exists hbm_sim] == 0} {
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set hbm_sim 0
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}
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set i_util_hbm_ip [get_bd_cells $i_util_hbm]
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set segments_per_master [get_property CONFIG.HBM_SEGMENTS_PER_MASTER $i_util_hbm_ip]
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set num_m [get_property CONFIG.NUM_M $i_util_hbm_ip]
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if {$hbm_sim == 0} {
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set i_hbm_ip [get_bd_cells $i_hbm]
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set num_stacks [get_property CONFIG.USER_HBM_STACK $i_hbm_ip]
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# 16 pseudo channels / sections / segments per stack
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set num_segments [expr $num_stacks*16]
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set totat_used_segments [expr $num_m * $segments_per_master]
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for {set i 0} {$i < $totat_used_segments} {incr i} {
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set idx_hbm_slv [format "%02d" [expr $i+$first_slave_index]]
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if {$i % $segments_per_master == 0} {
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ad_ip_parameter $i_hbm CONFIG.USER_SAXI_${idx_hbm_slv} {true}
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ad_connect $i_util_hbm/MAXI_[expr $i/$segments_per_master] $i_hbm/SAXI_${idx_hbm_slv}
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ad_connect $i_hbm/AXI_${idx_hbm_slv}_ACLK $axi_clk
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ad_connect $i_hbm/AXI_${idx_hbm_slv}_ARESET_N $axi_aresetn
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}
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}
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ad_ip_parameter $i_util_hbm CONFIG.HBM_SEGMENT_INDEX $first_slave_index
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} else {
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# Create smart connect
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ad_ip_instance smartconnect axi_hbm_interconnect [list \
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NUM_MI 1 \
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NUM_SI $num_m \
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]
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# connect it to hbm vip
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ad_connect axi_hbm_interconnect/M00_AXI $i_hbm/S_AXI
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# connect smart connect to util_hbm
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for {set i 0} {$i < $num_m} {incr i} {
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set i_formatted [format "%02d" $i]
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ad_connect $i_util_hbm/MAXI_$i axi_hbm_interconnect/S${i_formatted}_AXI
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}
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ad_connect axi_hbm_interconnect/aclk $axi_clk
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ad_connect axi_hbm_interconnect/aresetn $axi_aresetn
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ad_connect $i_hbm/aclk $axi_clk
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ad_connect $i_hbm/aresetn $axi_aresetn
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}
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ad_connect $axi_clk $i_util_hbm/m_axi_aclk
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ad_connect $axi_aresetn $i_util_hbm/m_axi_aresetn
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for {set i 0} {$i < $num_m} {incr i} {
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assign_bd_address -target_address_space $i_util_hbm/MAXI_${i}
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}
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}
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proc log2 {x} {
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return [tcl::mathfunc::int [tcl::mathfunc::ceil [expr [tcl::mathfunc::log $x] / [tcl::mathfunc::log 2]]]]
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}
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