Istvan Csomortani cdf01a492e library/axi_dacfifo: Update the bypass logic ... The bypass logic is located between the AXI read controller and the DAC CDC fifo. When the bypass is enabled the DMAC destination interface must be clocked with the PL_DDR controller's ui_clk. This way it can easily switch between the AXI read's stream and DMAC's stream interface.		2016-06-22 12:24:54 +03:00
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Makefile	hdl make updates	2016-06-01 13:53:09 -04:00
axi_dacfifo.v	library/axi_dacfifo: Update the bypass logic	2016-06-22 12:24:54 +03:00
axi_dacfifo_constr.xdc	library/axi_dacfifo: Update the bypass logic	2016-06-22 12:24:54 +03:00
axi_dacfifo_dac.v	axi_dacfifo: Cosmetic changes	2016-05-27 14:13:55 +03:00
axi_dacfifo_ip.tcl	library/axi_dacfifo: Update the bypass logic	2016-06-22 12:24:54 +03:00
axi_dacfifo_rd.v	axi_dacfifo: Cosmetic changes	2016-05-27 14:13:55 +03:00
axi_dacfifo_wr.v	library/axi_dacfifo: Fix the control logic of the write side	2016-06-15 13:49:00 +03:00