281 lines
9.3 KiB
Tcl
281 lines
9.3 KiB
Tcl
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# check tool version
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if {![info exists REQUIRED_VIVADO_VERSION]} {
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set REQUIRED_VIVADO_VERSION "2015.4.2"
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}
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if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
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set IGNORE_VERSION_CHECK 1
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} elseif {![info exists IGNORE_VERSION_CHECK]} {
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set IGNORE_VERSION_CHECK 0
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}
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# ip related stuff
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proc adi_ip_create {ip_name} {
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global ad_hdl_dir
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global ad_phdl_dir
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global REQUIRED_VIVADO_VERSION
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global IGNORE_VERSION_CHECK
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if {!$IGNORE_VERSION_CHECK && [string compare [version -short] $REQUIRED_VIVADO_VERSION] != 0} {
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return -code error [format "ERROR: This library requires Vivado %s." $REQUIRED_VIVADO_VERSION]
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}
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create_project $ip_name . -force
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set lib_dirs $ad_hdl_dir/library
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if {$ad_hdl_dir ne $ad_phdl_dir} {
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lappend lib_dirs $ad_phdl_dir/library
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}
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set_property ip_repo_paths $lib_dirs [current_fileset]
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update_ip_catalog
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set proj_dir [get_property directory [current_project]]
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set proj_name [get_projects $ip_name]
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}
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proc adi_ip_files {ip_name ip_files} {
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set proj_fileset [get_filesets sources_1]
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add_files -norecurse -scan_for_includes -fileset $proj_fileset $ip_files
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set_property "top" "$ip_name" $proj_fileset
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}
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proc adi_ip_constraints {ip_name ip_constr_files {processing_order late}} {
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set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
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foreach f_name $ip_constr_files {
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ipx::add_file $f_name $proj_filegroup
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set_property type xdc [ipx::get_files $f_name -of_objects $proj_filegroup]
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set_property processing_order $processing_order [ipx::get_files $f_name -of_objects $proj_filegroup]
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}
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}
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proc adi_ip_ttcl {ip_name ip_constr_files} {
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set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
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set f [ipx::add_file $ip_constr_files $proj_filegroup]
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set_property -dict [list \
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type ttcl \
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] $f
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}
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proc adi_ip_bd {ip_name ip_bd_files} {
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set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]]
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if {$proj_filegroup == {}} {
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set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]]
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}
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set f [ipx::add_file $ip_bd_files $proj_filegroup]
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set_property -dict [list \
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type tclSource \
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] $f
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}
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proc adi_ip_properties {ip_name} {
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adi_ip_properties_lite $ip_name
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ipx::infer_bus_interface {\
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s_axi_awvalid \
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s_axi_awaddr \
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s_axi_awprot \
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s_axi_awready \
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s_axi_wvalid \
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s_axi_wdata \
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s_axi_wstrb \
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s_axi_wready \
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s_axi_bvalid \
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s_axi_bresp \
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s_axi_bready \
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s_axi_arvalid \
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s_axi_araddr \
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s_axi_arprot \
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s_axi_arready \
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s_axi_rvalid \
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s_axi_rdata \
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s_axi_rresp \
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s_axi_rready} \
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xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::add_memory_map {s_axi} [ipx::current_core]
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set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
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ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
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set_property range {65536} [ipx::get_address_blocks axi_lite \
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-of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
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ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces s_axi_aclk \
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-of_objects [ipx::current_core]]
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set_property value s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
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-of_objects [ipx::get_bus_interfaces s_axi_aclk \
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-of_objects [ipx::current_core]]]
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ipx::infer_bus_interfaces xilinx.com:interface:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interfaces xilinx.com:interface:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
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}
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proc adi_ip_properties_lite {ip_name} {
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ipx::package_project -root_dir .
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set_property vendor {analog.com} [ipx::current_core]
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set_property library {user} [ipx::current_core]
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set_property taxonomy {{/AXI_Infrastructure}} [ipx::current_core]
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set_property vendor_display_name {Analog Devices} [ipx::current_core]
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set_property company_url {www.analog.com} [ipx::current_core]
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set_property supported_families {\
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virtex7 Production
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qvirtex7 Production
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kintex7 Production
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kintex7l Production
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qkintex7 Production
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qkintex7l Production
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artix7 Production
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artix7l Production
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aartix7 Production
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qartix7 Production
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zynq Production
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qzynq Production
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azynq Production
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virtexu Production
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kintexuplus Production
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zynquplus Production
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kintexu Production}\
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[ipx::current_core]
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ipx::remove_all_bus_interface [ipx::current_core]
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}
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proc adi_set_ports_dependency {port_prefix dependency} {
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foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
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set_property ENABLEMENT_DEPENDENCY $dependency $port
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}
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}
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proc adi_set_bus_dependency {bus prefix dependency} {
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set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]]
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adi_set_ports_dependency $prefix $dependency
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}
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proc adi_add_port_map {bus phys logic} {
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set map [ipx::add_port_map $phys $bus]
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set_property "PHYSICAL_NAME" $phys $map
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set_property "LOGICAL_NAME" $logic $map
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}
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proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
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set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
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set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
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set_property "BUS_TYPE_VLNV" $bus_type $bus
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set_property "INTERFACE_MODE" $mode $bus
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foreach port_map $port_maps {
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adi_add_port_map $bus {*}$port_map
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}
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}
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proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} {
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set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
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set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
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set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
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set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf
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set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf
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set_property display_name $clock_inf_name $clock_inf
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set clock_map [ipx::add_port_map "CLK" $clock_inf]
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set_property physical_name $clock_signal_name $clock_map
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set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf]
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set_property value $bus_inf_name $assoc_busif
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if { $reset_signal_name != "" } {
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set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf]
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set_property value $reset_signal_name $assoc_reset
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set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"]
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set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]]
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set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
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set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
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set_property display_name $reset_inf_name $reset_inf
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set_property interface_mode $reset_signal_mode $reset_inf
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set reset_map [ipx::add_port_map "RST" $reset_inf]
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set_property physical_name $reset_signal_name $reset_map
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set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf]
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set_property value "ACTIVE_LOW" $reset_polarity
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}
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}
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proc adi_ip_add_core_dependencies {vlnvs} {
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foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] {
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foreach vlnv $vlnvs {
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ipx::add_subcore $vlnv $file_group
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}
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}
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}
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proc adi_if_define {name} {
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ipx::create_abstraction_definition ADI user ${name}_rtl 1.0
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ipx::create_bus_definition ADI user $name 1.0
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set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs]
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set_property xml_file_name ${name}.xml [ipx::current_busdef]
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set_property bus_type_vlnv ADI:user:${name}:1.0 [ipx::current_busabs]
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ipx::save_abstraction_definition [ipx::current_busabs]
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ipx::save_bus_definition [ipx::current_busdef]
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}
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proc adi_if_ports {dir width name {type none}} {
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ipx::add_bus_abstraction_port $name [ipx::current_busabs]
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set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]]
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set_property master_presence required $m_intf
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set_property slave_presence required $m_intf
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set_property master_width $width $m_intf
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set_property slave_width $width $m_intf
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set m_dir "in"
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set s_dir "out"
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if {$dir eq "output"} {
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set m_dir "out"
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set s_dir "in"
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}
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set_property master_direction $m_dir $m_intf
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set_property slave_direction $s_dir $m_intf
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if {$type ne "none"} {
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set_property is_${type} true $m_intf
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}
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ipx::save_bus_definition [ipx::current_busdef]
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ipx::save_abstraction_definition [ipx::current_busabs]
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}
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proc adi_if_infer_bus {if_name mode name maps} {
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ipx::add_bus_interface $name [ipx::current_core]
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set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]]
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set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if
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set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if
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set_property interface_mode $mode $m_bus_if
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foreach map $maps {
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set m_maps [regexp -all -inline {\S+} $map]
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lassign $m_maps p_name p_map
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ipx::add_port_map $p_name $m_bus_if
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set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if]
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}
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}
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