PopPaul2021 e94df1d7da library/axi_ad7768: Data valid signal updates ... If the sampling clock is lower than dclk*number_of_active_lines*32 the interface should wait for the next adc_ready signal to reset the counter. The adc_valid_p signal should be set high just for a clock period after the sample was captured.		2023-03-01 15:52:05 +02:00
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Makefile	library & projects: Update Makefiles	2023-01-27 11:54:05 +02:00
axi_ad7768.v	Update IPs based on up_adc_common changes	2023-01-12 13:09:35 +02:00
axi_ad7768_hw.tcl	Added axi_ad7768 IP Core (#989)	2022-08-24 16:57:14 +03:00
axi_ad7768_if.v	library/axi_ad7768: Data valid signal updates	2023-03-01 15:52:05 +02:00
axi_ad7768_ip.tcl	Added axi_ad7768 IP Core (#989)	2022-08-24 16:57:14 +03:00