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Adrian Costina 0cb5c0bdaf adv9009zu11eg: Update FPGA to -2. Update DDR4 clock frequency 2019-11-27 16:27:44 +02:00
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Makefile adrv9009zu11eg: Add axi_sysid 2019-11-19 10:29:57 +02:00
system_bd.tcl adrv9009zu11eg: Add axi_sysid 2019-11-19 10:29:57 +02:00
system_project.tcl adv9009zu11eg: Update FPGA to -2. Update DDR4 clock frequency 2019-11-27 16:27:44 +02:00
system_top.v adrv9009_zu11eg_som: Change design partitioning 2019-11-14 15:25:23 +02:00