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pluto_hdl_adi/library/common
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Istvan Csomortani 4b08df9ed6 ad9361/tdd: Fix generation of tx_valid_* signals 
In FDD mode the tx_valid_* signals are generated inside the axi_ad9361_tx module, in function of
the selected dac data rate. In TDD mode, these signals are gated by the tdd_enable and tdd_tx_dp_en signals.
In other words, the tx_valid_* signals will be valid just when tdd_enable and tdd_tx_dp_en is active.
 		2015-06-08 16:23:32 +03:00
..
altera library- jesd-align port name change 2015-05-20 14:25:21 -04:00
ad_addsub.v ad9361_tdd: Some naming and hierarchical changes 2015-06-04 18:09:49 +03:00
ad_axi_ip_constr.sdc axi_ip- constraints: add rst path 2015-06-04 10:53:13 -04:00
ad_axis_dma_rx.v initial checkin 2014-02-28 14:26:22 -05:00
ad_axis_dma_tx.v initial checkin 2014-02-28 14:26:22 -05:00
ad_axis_inf_rx.v ad9625_plddr: PL DDR3 fixes 2014-07-23 19:34:44 +03:00
ad_csc_1.v initial checkin 2014-02-28 14:26:22 -05:00
ad_csc_1_add.v initial checkin 2014-02-28 14:26:22 -05:00
ad_csc_1_mul.v mult instances: consistent naming style 2014-03-12 15:42:47 -04:00
ad_csc_CrYCb2RGB.v imageon_zc706: Updates and fixes 2015-03-27 18:57:32 +02:00
ad_csc_RGB2CrYCb.v initial checkin 2014-02-28 14:26:22 -05:00
ad_datafmt.v initial checkin 2014-02-28 14:26:22 -05:00
ad_dcfilter.v ad_dcfilter: Fix filter loopback 2014-08-12 14:42:10 +03:00
ad_dds.v library: register map changes and for mathworks 2014-06-24 14:23:56 -04:00
ad_dds_1.v library: register map changes and for mathworks 2014-06-24 14:24:22 -04:00
ad_dds_sine.v library: register map changes and for mathworks 2014-06-24 14:23:56 -04:00
ad_gt_channel_1.v library- drp moved to up clock 2015-06-01 13:39:26 -04:00
ad_gt_common_1.v library- drp moved to up clock 2015-06-01 13:39:26 -04:00
ad_gt_es.v library- drp moved to up clock 2015-06-01 13:39:26 -04:00
ad_iobuf.v iobuf: do is a system-verilog keyword 2015-05-21 14:06:13 -04:00
ad_iqcor.v library: register map changes and for mathworks 2014-06-24 14:23:56 -04:00
ad_jesd_align.v axi_ad9671: Updated port names. Fixed synchronization of the rx_sof with the ad_jesd_align module, so that data valid is assigned correctly 2015-05-23 00:16:27 +03:00
ad_lvds_clk.v Remove executable flags from non-exectuable files 2014-09-09 15:05:06 +02:00
ad_lvds_in.v delay-cntrl: up-clk, direct access + tx 2015-05-18 14:28:20 -04:00
ad_lvds_out.v delay-cntrl: up-clk, direct access + tx 2015-05-18 14:28:20 -04:00
ad_mem.v initial checkin 2014-02-28 14:26:22 -05:00
ad_mem_asym.v common/mem: asymmetric version 2014-10-30 11:12:09 -04:00
ad_mmcm_drp.v library- drp moved to up clock 2015-06-01 13:39:26 -04:00
ad_mul.v library: register map changes and for mathworks 2014-06-24 14:23:56 -04:00
ad_mul_u16.v mult instances: consistent naming style 2014-03-12 15:42:47 -04:00
ad_pnmon.v Remove executable flags from non-exectuable files 2014-09-09 15:05:06 +02:00
ad_rst.v ad_rst: ultrascale -dual stage 2014-11-05 16:47:41 -05:00
ad_serdes_clk.v library- drp moved to up clock 2015-06-01 13:39:26 -04:00
ad_serdes_in.v axi_ad9434 : Update the IO delay interface 2015-05-22 19:47:09 +03:00
ad_serdes_out.v initial checkin 2014-02-28 14:26:22 -05:00
ad_ss_422to444.v common: Add color space sampling and color space conversion modules 2015-01-08 12:24:46 +02:00
ad_ss_444to422.v initial checkin 2014-02-28 14:26:22 -05:00
ad_tdd_control.v ad9361_tdd: Some naming and hierarchical changes 2015-06-04 18:09:49 +03:00
axi_ctrlif.vhd initial checkin 2014-02-28 14:26:22 -05:00
axi_streaming_dma_rx_fifo.vhd initial checkin 2014-02-28 14:26:22 -05:00
axi_streaming_dma_tx_fifo.vhd initial checkin 2014-02-28 14:26:22 -05:00
dma_fifo.vhd dma_fifo: Simplify FIFO WE condition 2015-04-16 17:48:22 +02:00
pl330_dma_fifo.vhd initial checkin 2014-02-28 14:26:22 -05:00
sync_bits.v library: Use common prefix for CDC signal names 2015-04-15 17:20:22 +02:00
sync_gray.v library: Use common prefix for CDC signal names 2015-04-15 17:20:22 +02:00
up_adc_channel.v up/constr: independent read/write and local constraints 2014-10-02 14:35:59 -04:00
up_adc_common.v library- drp moved to up clock 2015-06-01 13:39:26 -04:00
up_axi.v up_axi: Fix up_raddr/up_waddr port width 2014-12-01 13:22:28 +01:00
up_axis_dma_rx.v up/constr: independent read/write and local constraints 2014-10-02 14:35:59 -04:00
up_axis_dma_tx.v up/constr: independent read/write and local constraints 2014-10-02 14:35:59 -04:00
up_clkgen.v library- drp moved to up clock 2015-06-01 13:39:26 -04:00
up_clock_mon.v initial checkin 2014-02-28 14:26:22 -05:00
up_dac_channel.v up/constr: independent read/write and local constraints 2014-10-02 14:35:59 -04:00
up_dac_common.v library- drp moved to up clock 2015-06-01 13:39:26 -04:00
up_delay_cntrl.v delay-cntrl: up-clk, direct access + tx 2015-05-18 14:28:20 -04:00
up_drp_cntrl.v initial checkin 2014-02-28 14:26:22 -05:00
up_gt.v library- drp moved to up clock 2015-06-01 13:39:26 -04:00
up_hdmi_rx.v imageon: updates 2015-03-24 15:08:48 -04:00
up_hdmi_tx.v up/constr: independent read/write and local constraints 2014-10-02 14:35:59 -04:00
up_pmod.v cftl_cip: Add util_pmod_fmeter IP to library 2015-02-23 17:20:12 +02:00
up_tdd_cntrl.v ad9361/tdd: Fix generation of tx_valid_* signals 2015-06-08 16:23:32 +03:00
up_xfer_cntrl.v xfer-logic: stretch toggles to allow capture 2015-02-06 22:15:14 -05:00
up_xfer_status.v xfer-logic: stretch toggles to allow capture 2015-02-06 22:15:16 -05:00