pluto_hdl_adi/projects/adv7513/de10nano/system_constr.sdc

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create_clock -period "20.000 ns" -name sys_clk_50mhz [get_ports {sys_clk}]
create_clock -period "16.666 ns" -name usb_clk_60mhz [get_ports {usb1_clk}]
derive_pll_clocks
derive_clock_uncertainty