424 lines
15 KiB
Verilog
Executable File
424 lines
15 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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// clock and resets
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input sys_clk,
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input sys_resetn,
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// hps-ddr4 (32)
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input hps_ddr_ref_clk,
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output [ 0:0] hps_ddr_clk_p,
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output [ 0:0] hps_ddr_clk_n,
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output [ 16:0] hps_ddr_a,
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output [ 1:0] hps_ddr_ba,
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output [ 0:0] hps_ddr_bg,
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output [ 0:0] hps_ddr_cke,
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output [ 0:0] hps_ddr_cs_n,
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output [ 0:0] hps_ddr_odt,
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output [ 0:0] hps_ddr_reset_n,
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output [ 0:0] hps_ddr_act_n,
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output [ 0:0] hps_ddr_par,
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input [ 0:0] hps_ddr_alert_n,
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inout [ 3:0] hps_ddr_dqs_p,
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inout [ 3:0] hps_ddr_dqs_n,
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inout [ 31:0] hps_ddr_dq,
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inout [ 3:0] hps_ddr_dbi_n,
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input hps_ddr_rzq,
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// pl-ddr4
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input sys_ddr_ref_clk,
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output [ 0:0] sys_ddr_clk_p,
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output [ 0:0] sys_ddr_clk_n,
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output [ 16:0] sys_ddr_a,
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output [ 1:0] sys_ddr_ba,
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output [ 0:0] sys_ddr_bg,
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output [ 0:0] sys_ddr_cke,
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output [ 0:0] sys_ddr_cs_n,
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output [ 0:0] sys_ddr_odt,
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output [ 0:0] sys_ddr_reset_n,
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output [ 0:0] sys_ddr_act_n,
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output [ 0:0] sys_ddr_par,
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input [ 0:0] sys_ddr_alert_n,
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inout [ 7:0] sys_ddr_dqs_p,
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inout [ 7:0] sys_ddr_dqs_n,
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inout [ 63:0] sys_ddr_dq,
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inout [ 7:0] sys_ddr_dbi_n,
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input sys_ddr_rzq,
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// hps-ethernet
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input [ 0:0] hps_eth_rxclk,
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input [ 0:0] hps_eth_rxctl,
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input [ 3:0] hps_eth_rxd,
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output [ 0:0] hps_eth_txclk,
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output [ 0:0] hps_eth_txctl,
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output [ 3:0] hps_eth_txd,
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output [ 0:0] hps_eth_mdc,
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inout [ 0:0] hps_eth_mdio,
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// hps-sdio
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output [ 0:0] hps_sdio_clk,
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inout [ 0:0] hps_sdio_cmd,
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inout [ 7:0] hps_sdio_d,
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// hps-usb
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input [ 0:0] hps_usb_clk,
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input [ 0:0] hps_usb_dir,
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input [ 0:0] hps_usb_nxt,
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output [ 0:0] hps_usb_stp,
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inout [ 7:0] hps_usb_d,
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// hps-uart
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input [ 0:0] hps_uart_rx,
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output [ 0:0] hps_uart_tx,
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// hps-i2c (shared w fmc-a, fmc-b)
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inout [ 0:0] hps_i2c_sda,
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inout [ 0:0] hps_i2c_scl,
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// hps-gpio (max-v-u16)
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inout [ 3:0] hps_gpio,
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// gpio (max-v-u21)
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input [ 7:0] gpio_bd_i,
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output [ 3:0] gpio_bd_o,
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// adrv9009-interface
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input ref_clk_c,
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input core_clk_c,
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input [ 3:0] rx_serial_data_c,
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output [ 3:0] tx_serial_data_c,
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output rx_sync_c,
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output rx_os_sync_c,
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input tx_sync_c,
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input tx_sync_c_1,
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input sysref_c,
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output adrv9009_tx1_enable_c,
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output adrv9009_tx2_enable_c,
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output adrv9009_rx1_enable_c,
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output adrv9009_rx2_enable_c,
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output adrv9009_reset_b_c,
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input adrv9009_gpint_c,
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inout adrv9009_gpio_00_c,
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inout adrv9009_gpio_01_c,
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inout adrv9009_gpio_02_c,
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inout adrv9009_gpio_03_c,
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inout adrv9009_gpio_04_c,
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inout adrv9009_gpio_05_c,
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inout adrv9009_gpio_06_c,
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inout adrv9009_gpio_07_c,
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inout adrv9009_gpio_08_c,
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input ref_clk_d,
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input core_clk_d,
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input [ 3:0] rx_serial_data_d,
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output [ 3:0] tx_serial_data_d,
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output rx_sync_d,
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output rx_os_sync_d,
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input tx_sync_d,
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input tx_sync_d_1,
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input sysref_d,
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output adrv9009_tx1_enable_d,
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output adrv9009_tx2_enable_d,
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output adrv9009_rx1_enable_d,
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output adrv9009_rx2_enable_d,
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output adrv9009_reset_b_d,
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input adrv9009_gpint_d,
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inout adrv9009_gpio_00_d,
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inout adrv9009_gpio_01_d,
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inout adrv9009_gpio_02_d,
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inout adrv9009_gpio_03_d,
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inout adrv9009_gpio_04_d,
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inout adrv9009_gpio_05_d,
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inout adrv9009_gpio_06_d,
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inout adrv9009_gpio_07_d,
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inout adrv9009_gpio_08_d,
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input fan_tach,
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input fan_pwm,
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output hmc7044_reset,
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output hmc7044_sync,
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inout hmc7044_gpio_1,
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inout hmc7044_gpio_2,
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inout hmc7044_gpio_3,
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inout hmc7044_gpio_4,
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output spi_csn_hmc7044,
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output spi_csn_adrv9009_c,
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output spi_csn_adrv9009_d,
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output spi_clk,
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inout spi_sdio,
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input spi_miso);
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// internal signals
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wire sys_ddr_cal_success;
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wire sys_ddr_cal_fail;
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wire sys_hps_resetn;
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wire sys_resetn_s;
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wire [ 63:0] gpio_i;
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wire [ 63:0] gpio_o;
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wire [ 7:0] spi_csn_s;
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wire dac_fifo_bypass;
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wire spi_mosi;
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wire spi0_miso;
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wire rx_sync;
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wire rx_os_sync;
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wire tx_sync;
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wire [ 22:0] fmcomms8_gpio;
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// assignments
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assign spi_csn_adrv9009_c = spi_csn_s[0];
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assign spi_csn_adrv9009_d = spi_csn_s[1];
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assign spi_csn_hmc7044 = spi_csn_s[2];
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fmcomms8_spi i_spi (
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.spi_csn(spi_csn_s),
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.spi_clk(spi_clk),
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.spi_mosi(spi_mosi),
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.spi_miso_i(spi_miso),
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.spi_miso_o(spi0_miso),
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.spi_sdio(spi_sdio));
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assign rx_sync_c = rx_sync;
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assign rx_sync_d = rx_sync;
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assign rx_os_sync_c = rx_os_sync;
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assign rx_os_sync_d = rx_os_sync;
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assign tx_sync = tx_sync_c & tx_sync_d;
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assign adrv9009_gpio_00_c = fmcomms8_gpio[0];
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assign adrv9009_gpio_01_c = fmcomms8_gpio[1];
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assign adrv9009_gpio_02_c = fmcomms8_gpio[2];
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assign adrv9009_gpio_03_c = fmcomms8_gpio[3];
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assign adrv9009_gpio_04_c = fmcomms8_gpio[4];
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assign adrv9009_gpio_05_c = fmcomms8_gpio[5];
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assign adrv9009_gpio_06_c = fmcomms8_gpio[6];
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assign adrv9009_gpio_07_c = fmcomms8_gpio[7];
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assign adrv9009_gpio_08_c = fmcomms8_gpio[8];
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assign adrv9009_gpio_00_d = fmcomms8_gpio[9];
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assign adrv9009_gpio_01_d = fmcomms8_gpio[10];
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assign adrv9009_gpio_02_d = fmcomms8_gpio[11];
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assign adrv9009_gpio_03_d = fmcomms8_gpio[12];
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assign adrv9009_gpio_04_d = fmcomms8_gpio[13];
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assign adrv9009_gpio_05_d = fmcomms8_gpio[14];
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assign adrv9009_gpio_06_d = fmcomms8_gpio[15];
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assign adrv9009_gpio_07_d = fmcomms8_gpio[16];
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assign adrv9009_gpio_08_d = fmcomms8_gpio[17];
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assign hmc7044_gpio_1 = fmcomms8_gpio[18];
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assign hmc7044_gpio_2 = fmcomms8_gpio[19];
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assign hmc7044_gpio_3 = fmcomms8_gpio[20];
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assign hmc7044_gpio_4 = fmcomms8_gpio[21];
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assign hmc7044_reset = gpio_o[45];
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assign hmc7044_sync = gpio_o[46];
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assign adrv9009_tx1_enable_d = gpio_o[39];
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assign adrv9009_tx2_enable_d = gpio_o[40];
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assign adrv9009_rx1_enable_d = gpio_o[41];
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assign adrv9009_rx2_enable_d = gpio_o[42];
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assign adrv9009_reset_b_d = gpio_o[43];
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assign gpio_i[44] = adrv9009_gpint_d;
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assign adrv9009_tx1_enable_c = gpio_o[33];
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assign adrv9009_tx2_enable_c = gpio_o[34];
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assign adrv9009_rx1_enable_c = gpio_o[35];
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assign adrv9009_rx2_enable_c = gpio_o[36];
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assign adrv9009_reset_b_c = gpio_o[37];
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assign gpio_i[38] = adrv9009_gpint_c;
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assign dac_fifo_bypass = gpio_o[32];
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assign gpio_i[63:45] = gpio_o[63:45];
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assign gpio_i[43:39] = gpio_o[43:39];
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assign gpio_i[37:32] = gpio_o[37:32];
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// board stuff (max-v-u21)
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assign gpio_i[31:14] = gpio_o[31:14];
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assign gpio_i[13:13] = sys_ddr_cal_success;
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assign gpio_i[12:12] = sys_ddr_cal_fail;
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assign gpio_i[11: 4] = gpio_bd_i;
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assign gpio_i[ 3: 0] = gpio_o[3:0];
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assign gpio_bd_o = gpio_o[3:0];
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// peripheral reset
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assign sys_resetn_s = sys_resetn & sys_hps_resetn;
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// instantiations
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system_bd i_system_bd (
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.sys_clk_clk (sys_clk),
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.sys_ddr_mem_mem_ck (sys_ddr_clk_p),
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.sys_ddr_mem_mem_ck_n (sys_ddr_clk_n),
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.sys_ddr_mem_mem_a (sys_ddr_a),
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.sys_ddr_mem_mem_act_n (sys_ddr_act_n),
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.sys_ddr_mem_mem_ba (sys_ddr_ba),
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.sys_ddr_mem_mem_bg (sys_ddr_bg),
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.sys_ddr_mem_mem_cke (sys_ddr_cke),
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.sys_ddr_mem_mem_cs_n (sys_ddr_cs_n),
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.sys_ddr_mem_mem_odt (sys_ddr_odt),
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.sys_ddr_mem_mem_reset_n (sys_ddr_reset_n),
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.sys_ddr_mem_mem_par (sys_ddr_par),
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.sys_ddr_mem_mem_alert_n (sys_ddr_alert_n),
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.sys_ddr_mem_mem_dqs (sys_ddr_dqs_p),
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.sys_ddr_mem_mem_dqs_n (sys_ddr_dqs_n),
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.sys_ddr_mem_mem_dq (sys_ddr_dq),
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.sys_ddr_mem_mem_dbi_n (sys_ddr_dbi_n),
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.sys_ddr_oct_oct_rzqin (sys_ddr_rzq),
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.sys_ddr_ref_clk_clk (sys_ddr_ref_clk),
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.sys_ddr_status_local_cal_success (sys_ddr_cal_success),
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.sys_ddr_status_local_cal_fail (sys_ddr_cal_fail),
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.sys_gpio_bd_in_port (gpio_i[31:0]),
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.sys_gpio_bd_out_port (gpio_o[31:0]),
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.sys_gpio_in_export (gpio_i[63:32]),
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.sys_gpio_out_export (gpio_o[63:32]),
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.sys_hps_ddr_mem_ck (hps_ddr_clk_p),
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.sys_hps_ddr_mem_ck_n (hps_ddr_clk_n),
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.sys_hps_ddr_mem_a (hps_ddr_a),
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.sys_hps_ddr_mem_act_n (hps_ddr_act_n),
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.sys_hps_ddr_mem_ba (hps_ddr_ba),
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.sys_hps_ddr_mem_bg (hps_ddr_bg),
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.sys_hps_ddr_mem_cke (hps_ddr_cke),
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.sys_hps_ddr_mem_cs_n (hps_ddr_cs_n),
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.sys_hps_ddr_mem_odt (hps_ddr_odt),
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.sys_hps_ddr_mem_reset_n (hps_ddr_reset_n),
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.sys_hps_ddr_mem_par (hps_ddr_par),
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.sys_hps_ddr_mem_alert_n (hps_ddr_alert_n),
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.sys_hps_ddr_mem_dqs (hps_ddr_dqs_p),
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.sys_hps_ddr_mem_dqs_n (hps_ddr_dqs_n),
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.sys_hps_ddr_mem_dq (hps_ddr_dq),
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.sys_hps_ddr_mem_dbi_n (hps_ddr_dbi_n),
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.sys_hps_ddr_oct_oct_rzqin (hps_ddr_rzq),
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.sys_hps_ddr_ref_clk_clk (hps_ddr_ref_clk),
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.sys_hps_ddr_rstn_reset_n (sys_resetn),
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.sys_hps_io_hps_io_phery_emac0_TX_CLK (hps_eth_txclk),
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.sys_hps_io_hps_io_phery_emac0_TXD0 (hps_eth_txd[0]),
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.sys_hps_io_hps_io_phery_emac0_TXD1 (hps_eth_txd[1]),
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.sys_hps_io_hps_io_phery_emac0_TXD2 (hps_eth_txd[2]),
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.sys_hps_io_hps_io_phery_emac0_TXD3 (hps_eth_txd[3]),
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.sys_hps_io_hps_io_phery_emac0_RX_CTL (hps_eth_rxctl),
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.sys_hps_io_hps_io_phery_emac0_TX_CTL (hps_eth_txctl),
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.sys_hps_io_hps_io_phery_emac0_RX_CLK (hps_eth_rxclk),
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.sys_hps_io_hps_io_phery_emac0_RXD0 (hps_eth_rxd[0]),
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.sys_hps_io_hps_io_phery_emac0_RXD1 (hps_eth_rxd[1]),
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.sys_hps_io_hps_io_phery_emac0_RXD2 (hps_eth_rxd[2]),
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.sys_hps_io_hps_io_phery_emac0_RXD3 (hps_eth_rxd[3]),
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.sys_hps_io_hps_io_phery_emac0_MDIO (hps_eth_mdio),
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.sys_hps_io_hps_io_phery_emac0_MDC (hps_eth_mdc),
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.sys_hps_io_hps_io_phery_sdmmc_CMD (hps_sdio_cmd),
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.sys_hps_io_hps_io_phery_sdmmc_D0 (hps_sdio_d[0]),
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.sys_hps_io_hps_io_phery_sdmmc_D1 (hps_sdio_d[1]),
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.sys_hps_io_hps_io_phery_sdmmc_D2 (hps_sdio_d[2]),
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.sys_hps_io_hps_io_phery_sdmmc_D3 (hps_sdio_d[3]),
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.sys_hps_io_hps_io_phery_sdmmc_D4 (hps_sdio_d[4]),
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.sys_hps_io_hps_io_phery_sdmmc_D5 (hps_sdio_d[5]),
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.sys_hps_io_hps_io_phery_sdmmc_D6 (hps_sdio_d[6]),
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.sys_hps_io_hps_io_phery_sdmmc_D7 (hps_sdio_d[7]),
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.sys_hps_io_hps_io_phery_sdmmc_CCLK (hps_sdio_clk),
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.sys_hps_io_hps_io_phery_usb0_DATA0 (hps_usb_d[0]),
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.sys_hps_io_hps_io_phery_usb0_DATA1 (hps_usb_d[1]),
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.sys_hps_io_hps_io_phery_usb0_DATA2 (hps_usb_d[2]),
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.sys_hps_io_hps_io_phery_usb0_DATA3 (hps_usb_d[3]),
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.sys_hps_io_hps_io_phery_usb0_DATA4 (hps_usb_d[4]),
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.sys_hps_io_hps_io_phery_usb0_DATA5 (hps_usb_d[5]),
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.sys_hps_io_hps_io_phery_usb0_DATA6 (hps_usb_d[6]),
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.sys_hps_io_hps_io_phery_usb0_DATA7 (hps_usb_d[7]),
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.sys_hps_io_hps_io_phery_usb0_CLK (hps_usb_clk),
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.sys_hps_io_hps_io_phery_usb0_STP (hps_usb_stp),
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.sys_hps_io_hps_io_phery_usb0_DIR (hps_usb_dir),
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.sys_hps_io_hps_io_phery_usb0_NXT (hps_usb_nxt),
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.sys_hps_io_hps_io_phery_uart1_RX (hps_uart_rx),
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.sys_hps_io_hps_io_phery_uart1_TX (hps_uart_tx),
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.sys_hps_io_hps_io_phery_i2c1_SDA (hps_i2c_sda),
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.sys_hps_io_hps_io_phery_i2c1_SCL (hps_i2c_scl),
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.sys_hps_io_hps_io_gpio_gpio1_io5 (hps_gpio[0]),
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.sys_hps_io_hps_io_gpio_gpio1_io14 (hps_gpio[1]),
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.sys_hps_io_hps_io_gpio_gpio1_io16 (hps_gpio[2]),
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.sys_hps_io_hps_io_gpio_gpio1_io17 (hps_gpio[3]),
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.sys_hps_out_rstn_reset_n (sys_hps_resetn),
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.sys_hps_rstn_reset_n (sys_resetn),
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.sys_rstn_reset_n (sys_resetn_s),
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.sys_spi_MISO (spi0_miso),
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|
.sys_spi_MOSI (spi_mosi),
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.sys_spi_SCLK (spi_clk),
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.sys_spi_SS_n (spi_csn_s),
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.tx_serial_data_tx_serial_data ({tx_serial_data_d,tx_serial_data_c}),
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.tx_fifo_bypass_bypass (dac_fifo_bypass),
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.fmcomms8_gpio_export (fmcomms8_gpio),
|
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.core_clk_c_clk (core_clk_c),
|
|
.core_clk_d_clk (core_clk_d),
|
|
.tx_ref_clk_clk (ref_clk_c),
|
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.tx_sync_export (tx_sync),
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.tx_sysref_export (sysref_c),
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.rx_serial_data_rx_serial_data ({rx_serial_data_d[1:0],rx_serial_data_c[1:0]}),
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|
.rx_os_serial_data_rx_serial_data ({rx_serial_data_d[3:2],rx_serial_data_c[3:2]}),
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.rx_os_ref_clk_clk (ref_clk_c),
|
|
.rx_os_sync_export (rx_os_sync),
|
|
.rx_os_sysref_export (sysref_c),
|
|
.rx_ref_clk_clk (ref_clk_d),
|
|
.rx_sync_export (rx_sync),
|
|
.rx_sysref_export (sysref_c));
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|
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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