178 lines
5.5 KiB
Tcl
178 lines
5.5 KiB
Tcl
###############################################################################
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## Copyright (C) 2019-2024 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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##--------------------------------------------------------------
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# IMPORTANT: Set AD7616 operation and interface mode
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#
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# The get_env_param procedure retrieves parameter value from the environment if exists,
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# other case returns the default value specified in its second parameter field.
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#
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# How to use over-writable parameters from the environment:
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#
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# e.g.
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# make SER_PAR_N=0
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#
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# SER_PAR_N - Defines the interface type (serial OR parallel)
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# - Default value is 1
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#
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# LEGEND: Serial - 1
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# Parallel - 0
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#
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# NOTE : This switch is a 'hardware' switch. Please rebuild the design if the
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# variable has been changed.
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# SL5 - mounted - Serial
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# SL5 - unmounted - Parallel
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#
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##--------------------------------------------------------------
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set SER_PAR_N $ad_project_params(SER_PAR_N)
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puts "build parameters: SER_PAR_N: $SER_PAR_N"
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# control lines
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create_bd_port -dir O rx_cnvst
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create_bd_port -dir I rx_busy
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# instantiation
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# dma
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ad_ip_instance axi_dmac axi_ad7616_dma
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ad_ip_parameter axi_ad7616_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_ad7616_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_ad7616_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_ad7616_dma CONFIG.DMA_DATA_WIDTH_DEST 64
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# axi_pwm_gen
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ad_ip_instance axi_pwm_gen ad7616_pwm_gen
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ad_ip_parameter ad7616_pwm_gen CONFIG.PULSE_0_PERIOD 100
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ad_ip_parameter ad7616_pwm_gen CONFIG.PULSE_0_WIDTH 5
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ad_ip_parameter ad7616_pwm_gen CONFIG.ASYNC_CLK_EN 1
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# axi_clkgen
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ad_ip_instance axi_clkgen spi_clkgen
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ad_ip_parameter spi_clkgen CONFIG.CLK0_DIV 6
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ad_ip_parameter spi_clkgen CONFIG.VCO_DIV 1
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ad_ip_parameter spi_clkgen CONFIG.VCO_MUL 6
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# trigger to BUSY's negative edge
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create_bd_cell -type module -reference sync_bits busy_sync
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create_bd_cell -type module -reference ad_edge_detect busy_capture
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set_property -dict [list CONFIG.EDGE 1] [get_bd_cells busy_capture]
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ad_connect spi_clk busy_capture/clk
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ad_connect busy_capture/rst GND
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ad_connect spi_clk busy_sync/out_clk
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ad_connect busy_sync/in_bits rx_busy
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ad_connect busy_sync/out_bits busy_capture/signal_in
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if {$SER_PAR_N == 1} {
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create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 ad7616_spi
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source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
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set data_width 16
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set async_spi_clk 1
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set num_cs 1
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set num_sdi 2
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set sdi_delay 1
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set hier_spi_engine spi_ad7616
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spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $sdi_delay
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ad_ip_parameter axi_ad7616_dma CONFIG.DMA_DATA_WIDTH_SRC 32
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ad_ip_parameter axi_ad7616_dma CONFIG.DMA_TYPE_SRC 1
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ad_ip_parameter axi_ad7616_dma CONFIG.SYNC_TRANSFER_START 0
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ad_ip_parameter axi_ad7616_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_ad7616_dma CONFIG.AXI_SLICE_DEST 1
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# interface connections
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ad_connect $sys_cpu_clk $hier_spi_engine/clk
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ad_connect spi_clk $hier_spi_engine/spi_clk
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ad_connect sys_cpu_resetn $hier_spi_engine/resetn
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ad_connect $hier_spi_engine/m_spi ad7616_spi
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ad_connect spi_clk axi_ad7616_dma/s_axis_aclk
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ad_connect axi_ad7616_dma/s_axis $hier_spi_engine/m_axis_sample
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ad_connect busy_sync/out_resetn $hier_spi_engine/${hier_spi_engine}_axi_regmap/spi_resetn
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ad_connect busy_capture/signal_out $hier_spi_engine/${hier_spi_engine}_offload/trigger
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# interconnect
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ad_cpu_interconnect 0x44A00000 $hier_spi_engine/${hier_spi_engine}_axi_regmap
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# interrupts
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ad_cpu_interrupt ps-12 mb-12 /$hier_spi_engine/irq
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} else {
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# data interfaces
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create_bd_port -dir O -from 15 -to 0 rx_db_o
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create_bd_port -dir I -from 15 -to 0 rx_db_i
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create_bd_port -dir O rx_db_t
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create_bd_port -dir O rx_rd_n
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create_bd_port -dir O rx_wr_n
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create_bd_port -dir O rx_cs_n
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ad_ip_parameter axi_ad7616_dma CONFIG.DMA_DATA_WIDTH_SRC 16
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ad_ip_parameter axi_ad7616_dma CONFIG.DMA_TYPE_SRC 2
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ad_ip_instance axi_ad7616 axi_ad7616
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# interface connections
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ad_connect rx_db_o axi_ad7616/rx_db_o
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ad_connect rx_db_i axi_ad7616/rx_db_i
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ad_connect rx_db_t axi_ad7616/rx_db_t
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ad_connect rx_rd_n axi_ad7616/rx_rd_n
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ad_connect rx_wr_n axi_ad7616/rx_wr_n
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ad_connect rx_cs_n axi_ad7616/rx_cs_n
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ad_connect $sys_cpu_clk axi_ad7616_dma/fifo_wr_clk
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ad_connect axi_ad7616/adc_valid axi_ad7616_dma/fifo_wr_en
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ad_connect axi_ad7616/adc_data axi_ad7616_dma/fifo_wr_din
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ad_connect axi_ad7616/adc_sync axi_ad7616_dma/fifo_wr_sync
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ad_connect busy_capture/signal_out axi_ad7616/rx_trigger
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ad_connect busy_sync/out_resetn sys_cpu_resetn
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# interconnect
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ad_cpu_interconnect 0x44A80000 axi_ad7616
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}
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# interface connections
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ad_connect $sys_cpu_clk spi_clkgen/clk
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ad_connect spi_clk spi_clkgen/clk_0
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ad_connect ad7616_pwm_gen/pwm_0 rx_cnvst
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ad_connect $sys_cpu_clk ad7616_pwm_gen/s_axi_aclk
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ad_connect sys_cpu_resetn ad7616_pwm_gen/s_axi_aresetn
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ad_connect spi_clk ad7616_pwm_gen/ext_clk
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ad_connect $sys_cpu_clk axi_ad7616_dma/s_axi_aclk
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ad_connect sys_cpu_resetn axi_ad7616_dma/m_dest_axi_aresetn
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# interconnect
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ad_cpu_interconnect 0x44A30000 axi_ad7616_dma
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ad_cpu_interconnect 0x44A70000 spi_clkgen
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ad_cpu_interconnect 0x44B00000 ad7616_pwm_gen
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# memory interconnect
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ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1
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ad_mem_hp1_interconnect $sys_cpu_clk axi_ad7616_dma/m_dest_axi
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# interrupts
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ad_cpu_interrupt ps-13 mb-13 axi_ad7616_dma/irq
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