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Laszlo Nagy e76f287e73 ad9081_fmca_ebz:vcu128: Initial version 
* 4Txs / 4Rxs per MxFE
 * Tx I/Q Rate: 250 MSPS
 * Rx I/Q Rate: 250 MSPS
 * DAC JESD204B: Mode 9, L=4, M=8, N=N'=16
 * ADC JESD204B: Mode 10, L=4, M=8, N=N'=16
 * DAC-Side JESD204B Lane Rate: 10Gbps
 * ADC-Side JESD204B Lane Rate: 10Gbps
 		2021-11-19 18:08:16 +02:00
..
a10soc ad9081_fmca_ebz_qsys.tcl: Add RX_LANE_RATE and TX_LANE_RATE parameters 2021-11-12 13:04:57 +02:00
common ad9081_fmca_ebz: versal: Remove external gt_reset logic 2021-11-19 14:01:48 +02:00
vck190 ad9081_fmca_ebz: versal: Remove external gt_reset logic 2021-11-19 14:01:48 +02:00
vcu118 projects/ad9081_fmca_ebz: Updated makefiles 2021-10-05 16:56:57 +03:00
vcu128 ad9081_fmca_ebz:vcu128: Initial version 2021-11-19 18:08:16 +02:00
zc706 projects/ad9081_fmca_ebz: Updated makefiles 2021-10-05 16:56:57 +03:00
zcu102 projects/ad9081_fmca_ebz: Updated makefiles 2021-10-05 16:56:57 +03:00
Makefile Makefiles: Update header with the appropriate license 2021-09-16 16:50:53 +03:00
Readme.md start adding some doc to the ./projects directory 2021-11-10 14:01:06 +02:00

Readme.md

AD9081-FMCA-EBZ HDL Project

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