pluto_hdl_adi/projects/ad_fmclidar1_ebz/a10soc
Istvan Csomortani 03bec4b49c ad_fmclidar1_ebz: Interchange SYSREF and DEV_CLK ports location
In ZCU102 LA01_CC_P|N are connected to regional clock, but in order to
receive a device clock properly we have to use pin which is connected
to a  global clock buffer. Luckily SYSREF is connected to global clock
pin; swap to port to receive the device clock correctly.

Also, swap the ports in both ZC706 and A10SOC carriers.
2019-10-17 09:59:23 +03:00
..
Makefile ad_fmclidar1_ebz/a10soc: Initial commit 2019-10-02 15:32:17 +03:00
system_constr.sdc ad_fmclidar1_ebz/a10soc: Initial commit 2019-10-02 15:32:17 +03:00
system_project.tcl ad_fmclidar1_ebz: Interchange SYSREF and DEV_CLK ports location 2019-10-17 09:59:23 +03:00
system_qsys.tcl ad_fmclidar1_ebz/a10soc: Initial commit 2019-10-02 15:32:17 +03:00
system_top.v ad_fmclidar1_ebz/a10soc: Initial commit 2019-10-02 15:32:17 +03:00