345 lines
10 KiB
Verilog
345 lines
10 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2015(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ps
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module axi_ad9361_tdd (
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// clock
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clk,
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rst,
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// control signals from the tdd control
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tdd_rx_vco_en,
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tdd_tx_vco_en,
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tdd_rx_rf_en,
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tdd_tx_rf_en,
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// status signal
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tdd_enabled,
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tdd_status,
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// sync signal
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tdd_sync,
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tdd_sync_cntr,
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// tx/rx data flow control
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tx_valid,
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tx_valid_i0,
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tx_valid_q0,
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tx_valid_i1,
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tx_valid_q1,
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tdd_tx_valid,
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tdd_tx_valid_i0,
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tdd_tx_valid_q0,
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tdd_tx_valid_i1,
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tdd_tx_valid_q1,
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rx_valid_i0,
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rx_valid_q0,
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rx_valid_i1,
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rx_valid_q1,
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tdd_rx_valid_i0,
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tdd_rx_valid_q0,
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tdd_rx_valid_i1,
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tdd_rx_valid_q1,
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// bus interface
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up_rstn,
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up_clk,
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up_wreq,
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up_waddr,
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up_wdata,
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up_wack,
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up_rreq,
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up_raddr,
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up_rdata,
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up_rack,
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tdd_dbg
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);
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input clk;
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input rst;
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// control signals from the tdd control
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output tdd_rx_vco_en;
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output tdd_tx_vco_en;
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output tdd_rx_rf_en;
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output tdd_tx_rf_en;
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output tdd_enabled;
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input [ 7:0] tdd_status;
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input tdd_sync;
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output tdd_sync_cntr;
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// tx data flow control
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input tx_valid;
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input tx_valid_i0;
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input tx_valid_q0;
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input tx_valid_i1;
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input tx_valid_q1;
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output tdd_tx_valid;
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output tdd_tx_valid_i0;
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output tdd_tx_valid_q0;
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output tdd_tx_valid_i1;
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output tdd_tx_valid_q1;
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// rx data flow control
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input rx_valid_i0;
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input rx_valid_q0;
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input rx_valid_i1;
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input rx_valid_q1;
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output tdd_rx_valid_i0;
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output tdd_rx_valid_q0;
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output tdd_rx_valid_i1;
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output tdd_rx_valid_q1;
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// bus interface
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input up_rstn;
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input up_clk;
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input up_wreq;
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input [13:0] up_waddr;
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input [31:0] up_wdata;
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output up_wack;
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input up_rreq;
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input [13:0] up_raddr;
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output [31:0] up_rdata;
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output up_rack;
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output [41:0] tdd_dbg;
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reg tdd_slave_synced = 1'b0;
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reg tdd_tx_valid = 1'b0;
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reg tdd_tx_valid_i0 = 1'b0;
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reg tdd_tx_valid_q0 = 1'b0;
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reg tdd_tx_valid_i1 = 1'b0;
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reg tdd_tx_valid_q1 = 1'b0;
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reg tdd_rx_valid_i0 = 1'b0;
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reg tdd_rx_valid_q0 = 1'b0;
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reg tdd_rx_valid_i1 = 1'b0;
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reg tdd_rx_valid_q1 = 1'b0;
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// internal signals
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wire rst;
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wire tdd_enable_s;
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wire tdd_secondary_s;
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wire [ 7:0] tdd_burst_count_s;
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wire tdd_rx_only_s;
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wire tdd_tx_only_s;
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wire tdd_gated_rx_dmapath_s;
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wire tdd_gated_tx_dmapath_s;
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wire [23:0] tdd_counter_init_s;
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wire [23:0] tdd_frame_length_s;
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wire tdd_terminal_type_s;
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wire tdd_sync_enable_s;
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wire [23:0] tdd_vco_rx_on_1_s;
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wire [23:0] tdd_vco_rx_off_1_s;
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wire [23:0] tdd_vco_tx_on_1_s;
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wire [23:0] tdd_vco_tx_off_1_s;
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wire [23:0] tdd_rx_on_1_s;
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wire [23:0] tdd_rx_off_1_s;
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wire [23:0] tdd_tx_on_1_s;
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wire [23:0] tdd_tx_off_1_s;
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wire [23:0] tdd_tx_dp_on_1_s;
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wire [23:0] tdd_tx_dp_off_1_s;
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wire [23:0] tdd_vco_rx_on_2_s;
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wire [23:0] tdd_vco_rx_off_2_s;
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wire [23:0] tdd_vco_tx_on_2_s;
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wire [23:0] tdd_vco_tx_off_2_s;
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wire [23:0] tdd_rx_on_2_s;
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wire [23:0] tdd_rx_off_2_s;
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wire [23:0] tdd_tx_on_2_s;
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wire [23:0] tdd_tx_off_2_s;
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wire [23:0] tdd_tx_dp_on_2_s;
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wire [23:0] tdd_tx_dp_off_2_s;
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wire [23:0] tdd_counter_status;
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wire tdd_tx_dp_en_s;
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assign tdd_dbg = {tdd_counter_status, tdd_enable_s, tdd_sync, tdd_tx_dp_en_s,
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tdd_rx_vco_en, tdd_tx_vco_en, tdd_rx_rf_en, tdd_tx_rf_en};
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assign tdd_enabled = tdd_enable_s;
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assign tdd_sync_cntr = ~(tdd_enable_s & tdd_terminal_type_s);
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// tx/rx data flow control
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always @(posedge clk) begin
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if((tdd_enable_s == 1) && (tdd_gated_tx_dmapath_s == 1)) begin
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tdd_tx_valid <= tx_valid & tdd_tx_dp_en_s;
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tdd_tx_valid_i0 <= tx_valid_i0 & tdd_tx_dp_en_s;
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tdd_tx_valid_q0 <= tx_valid_q0 & tdd_tx_dp_en_s;
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tdd_tx_valid_i1 <= tx_valid_i1 & tdd_tx_dp_en_s;
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tdd_tx_valid_q1 <= tx_valid_q1 & tdd_tx_dp_en_s;
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end else begin
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tdd_tx_valid <= tx_valid;
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tdd_tx_valid_i0 <= tx_valid_i0;
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tdd_tx_valid_q0 <= tx_valid_q0;
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tdd_tx_valid_i1 <= tx_valid_i1;
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tdd_tx_valid_q1 <= tx_valid_q1;
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end
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end
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always @(posedge clk) begin
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if((tdd_enable_s == 1) && (tdd_gated_tx_dmapath_s == 1)) begin
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tdd_rx_valid_i0 <= rx_valid_i0 & tdd_rx_rf_en;
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tdd_rx_valid_q0 <= rx_valid_q0 & tdd_rx_rf_en;
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tdd_rx_valid_i1 <= rx_valid_i1 & tdd_rx_rf_en;
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tdd_rx_valid_q1 <= rx_valid_q1 & tdd_rx_rf_en;
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end else begin
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tdd_rx_valid_i0 <= rx_valid_i0;
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tdd_rx_valid_q0 <= rx_valid_q0;
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tdd_rx_valid_i1 <= rx_valid_i1;
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tdd_rx_valid_q1 <= rx_valid_q1;
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end
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end
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// instantiations
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up_tdd_cntrl i_up_tdd_cntrl(
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.clk(clk),
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.rst(rst),
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.tdd_enable(tdd_enable_s),
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.tdd_secondary(tdd_secondary_s),
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.tdd_burst_count(tdd_burst_count_s),
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.tdd_tx_only(tdd_tx_only_s),
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.tdd_rx_only(tdd_rx_only_s),
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.tdd_gated_rx_dmapath(tdd_gated_rx_dmapath_s),
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.tdd_gated_tx_dmapath(tdd_gated_tx_dmapath_s),
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.tdd_counter_init(tdd_counter_init_s),
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.tdd_frame_length(tdd_frame_length_s),
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.tdd_terminal_type(tdd_terminal_type_s),
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.tdd_vco_rx_on_1(tdd_vco_rx_on_1_s),
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.tdd_vco_rx_off_1(tdd_vco_rx_off_1_s),
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.tdd_vco_tx_on_1(tdd_vco_tx_on_1_s),
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.tdd_vco_tx_off_1(tdd_vco_tx_off_1_s),
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.tdd_rx_on_1(tdd_rx_on_1_s),
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.tdd_rx_off_1(tdd_rx_off_1_s),
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.tdd_tx_on_1(tdd_tx_on_1_s),
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.tdd_tx_off_1(tdd_tx_off_1_s),
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.tdd_tx_dp_on_1(tdd_tx_dp_on_1_s),
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.tdd_tx_dp_off_1(tdd_tx_dp_off_1_s),
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.tdd_vco_rx_on_2(tdd_vco_rx_on_2_s),
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.tdd_vco_rx_off_2(tdd_vco_rx_off_2_s),
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.tdd_vco_tx_on_2(tdd_vco_tx_on_2_s),
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.tdd_vco_tx_off_2(tdd_vco_tx_off_2_s),
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.tdd_rx_on_2(tdd_rx_on_2_s),
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.tdd_rx_off_2(tdd_rx_off_2_s),
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.tdd_tx_on_2(tdd_tx_on_2_s),
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.tdd_tx_off_2(tdd_tx_off_2_s),
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.tdd_tx_dp_on_2(tdd_tx_dp_on_2_s),
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.tdd_tx_dp_off_2(tdd_tx_dp_off_2_s),
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.tdd_status(tdd_status),
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.up_rstn(up_rstn),
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.up_clk(up_clk),
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.up_wreq(up_wreq),
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.up_waddr(up_waddr),
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.up_wdata(up_wdata),
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.up_wack(up_wack),
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.up_rreq(up_rreq),
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.up_raddr(up_raddr),
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.up_rdata(up_rdata),
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.up_rack(up_rack));
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// the TX_DATA_PATH_DELAY and CONTROL_PATH_DELAY are specificly defined
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// for the axi_ad9361 core
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ad_tdd_control #(
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.TX_DATA_PATH_DELAY(14),
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.CONTROL_PATH_DELAY(3))
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i_tdd_control(
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.clk(clk),
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.rst(rst),
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.tdd_enable(tdd_enable_s),
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.tdd_secondary(tdd_secondary_s),
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.tdd_counter_init(tdd_counter_init_s),
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.tdd_frame_length(tdd_frame_length_s),
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.tdd_burst_count(tdd_burst_count_s),
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.tdd_rx_only(tdd_rx_only_s),
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.tdd_tx_only(tdd_tx_only_s),
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.tdd_sync (tdd_sync),
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.tdd_vco_rx_on_1(tdd_vco_rx_on_1_s),
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.tdd_vco_rx_off_1(tdd_vco_rx_off_1_s),
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.tdd_vco_tx_on_1(tdd_vco_tx_on_1_s),
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.tdd_vco_tx_off_1(tdd_vco_tx_off_1_s),
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.tdd_rx_on_1(tdd_rx_on_1_s),
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.tdd_rx_off_1(tdd_rx_off_1_s),
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.tdd_tx_on_1(tdd_tx_on_1_s),
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.tdd_tx_off_1(tdd_tx_off_1_s),
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.tdd_tx_dp_on_1(tdd_tx_dp_on_1_s),
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.tdd_tx_dp_off_1(tdd_tx_dp_off_1_s),
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.tdd_vco_rx_on_2(tdd_vco_rx_on_2_s),
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.tdd_vco_rx_off_2(tdd_vco_rx_off_2_s),
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.tdd_vco_tx_on_2(tdd_vco_tx_on_2_s),
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.tdd_vco_tx_off_2(tdd_vco_tx_off_2_s),
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.tdd_rx_on_2(tdd_rx_on_2_s),
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.tdd_rx_off_2(tdd_rx_off_2_s),
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.tdd_tx_on_2(tdd_tx_on_2_s),
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.tdd_tx_off_2(tdd_tx_off_2_s),
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.tdd_tx_dp_on_2(tdd_tx_dp_on_2_s),
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.tdd_tx_dp_off_2(tdd_tx_dp_off_2_s),
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.tdd_tx_dp_en(tdd_tx_dp_en_s),
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.tdd_rx_vco_en(tdd_rx_vco_en),
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.tdd_tx_vco_en(tdd_tx_vco_en),
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.tdd_rx_rf_en(tdd_rx_rf_en),
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.tdd_tx_rf_en(tdd_tx_rf_en),
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.tdd_counter_status(tdd_counter_status));
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endmodule
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