Adrian Costina 39ac29bb01 AD9361: Altera, modified address width so that all registers are accessible ... Modified qsys project with the new address span		2014-07-08 10:41:51 +03:00
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system_bd.qsys	AD9361: Altera, modified address width so that all registers are accessible	2014-07-08 10:41:51 +03:00
system_constr.sdc	fmcomms2/c5soc: initial checkin	2014-07-02 14:56:00 -04:00
system_project.tcl	fmcomms2/c5soc: Fixed the MOSI and MISO pin assignments.	2014-07-07 22:28:25 +03:00
system_timing.tcl	c5soc: initial a5soc copy	2014-07-01 13:09:38 -04:00
system_top.v	fmcomms2/c5soc: Fixed the spim0_ss_in_n value.	2014-07-08 10:07:31 +03:00