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AndreiGrozav cde9956948 ad4858_fmcz: Initial design 
Reference design for AD4858 20-bit, low noise 8-channel, SAR ADC with
buffered differential, wide common range picoamp inputs.

The design supports:
- CMOS and LVDS interfaces(at build time)
- Runtime sampling changes
- Store captured samples in RAM, through DMA (available via software support)

Documentation at: https://wiki.analog.com/resources/eval/user-guides/ad4858_fmcz/ad4858_fmcz_hdl
 		2023-10-05 10:19:03 +03:00
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common ad4858_fmcz: Initial design 2023-10-05 10:19:03 +03:00
zed ad4858_fmcz: Initial design 2023-10-05 10:19:03 +03:00
Makefile ad4858_fmcz: Initial design 2023-10-05 10:19:03 +03:00
Readme.md ad4858_fmcz: Initial design 2023-10-05 10:19:03 +03:00

Readme.md

AD4858 HDL Project

Here are some pointers to help you: