534 lines
19 KiB
Verilog
Executable File
534 lines
19 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// This interface includes both the transmit and receive components -
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// They both uses the same clock (sourced from the receiving side).
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`timescale 1ns/100ps
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module axi_ad9361_pnlb (
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// device interface
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clk,
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adc_valid_in,
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adc_data_in_i1,
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adc_data_in_q1,
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adc_data_in_i2,
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adc_data_in_q2,
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dac_valid_in,
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dac_data_in_i1,
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dac_data_in_q1,
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dac_data_in_i2,
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dac_data_in_q2,
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// dac outputs
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dac_valid,
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dac_data_i1,
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dac_data_q1,
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dac_data_i2,
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dac_data_q2,
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// control signals
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dac_lb_enb_i1,
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dac_pn_enb_i1,
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dac_lb_enb_q1,
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dac_pn_enb_q1,
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dac_lb_enb_i2,
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dac_pn_enb_i2,
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dac_lb_enb_q2,
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dac_pn_enb_q2,
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// status signals
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adc_pn_oos_i1,
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adc_pn_err_i1,
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adc_pn_oos_q1,
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adc_pn_err_q1,
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adc_pn_oos_i2,
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adc_pn_err_i2,
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adc_pn_oos_q2,
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adc_pn_err_q2);
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// device interface
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input clk;
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input adc_valid_in;
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input [11:0] adc_data_in_i1;
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input [11:0] adc_data_in_q1;
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input [11:0] adc_data_in_i2;
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input [11:0] adc_data_in_q2;
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input dac_valid_in;
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input [11:0] dac_data_in_i1;
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input [11:0] dac_data_in_q1;
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input [11:0] dac_data_in_i2;
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input [11:0] dac_data_in_q2;
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// dac outputs
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output dac_valid;
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output [11:0] dac_data_i1;
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output [11:0] dac_data_q1;
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output [11:0] dac_data_i2;
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output [11:0] dac_data_q2;
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// control signals
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input dac_lb_enb_i1;
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input dac_pn_enb_i1;
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input dac_lb_enb_q1;
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input dac_pn_enb_q1;
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input dac_lb_enb_i2;
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input dac_pn_enb_i2;
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input dac_lb_enb_q2;
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input dac_pn_enb_q2;
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// status signals
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output adc_pn_oos_i1;
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output adc_pn_err_i1;
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output adc_pn_oos_q1;
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output adc_pn_err_q1;
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output adc_pn_oos_i2;
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output adc_pn_err_i2;
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output adc_pn_oos_q2;
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output adc_pn_err_q2;
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// internal registers
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reg dac_valid_t = 'd0;
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reg [23:0] dac_pn_i1 = 'd0;
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reg [23:0] dac_pn_q1 = 'd0;
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reg [23:0] dac_pn_i2 = 'd0;
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reg [23:0] dac_pn_q2 = 'd0;
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reg [11:0] dac_lb_i1 = 'd0;
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reg [11:0] dac_lb_q1 = 'd0;
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reg [11:0] dac_lb_i2 = 'd0;
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reg [11:0] dac_lb_q2 = 'd0;
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reg dac_valid = 'd0;
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reg [11:0] dac_data_i1 = 'd0;
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reg [11:0] dac_data_q1 = 'd0;
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reg [11:0] dac_data_i2 = 'd0;
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reg [11:0] dac_data_q2 = 'd0;
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reg adc_valid_t = 'd0;
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reg [11:0] adc_data_in_i1_d = 'd0;
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reg [11:0] adc_data_in_q1_d = 'd0;
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reg [11:0] adc_data_in_i2_d = 'd0;
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reg [11:0] adc_data_in_q2_d = 'd0;
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reg [23:0] adc_pn_data_i1 = 'd0;
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reg [23:0] adc_pn_data_q1 = 'd0;
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reg [23:0] adc_pn_data_i2 = 'd0;
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reg [23:0] adc_pn_data_q2 = 'd0;
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reg adc_pn_err_i1 = 'd0;
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reg adc_pn_oos_i1 = 'd0;
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reg [ 3:0] adc_pn_oos_count_i1 = 'd0;
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reg adc_pn_err_q1 = 'd0;
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reg adc_pn_oos_q1 = 'd0;
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reg [ 3:0] adc_pn_oos_count_q1 = 'd0;
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reg adc_pn_err_i2 = 'd0;
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reg adc_pn_oos_i2 = 'd0;
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reg [ 3:0] adc_pn_oos_count_i2 = 'd0;
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reg adc_pn_err_q2 = 'd0;
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reg adc_pn_oos_q2 = 'd0;
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reg [ 3:0] adc_pn_oos_count_q2 = 'd0;
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// internal signals
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wire dac_valid_t_s;
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wire adc_valid_t_s;
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wire [23:0] adc_data_in_i1_s;
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wire adc_pn_err_i1_s;
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wire adc_pn_update_i1_s;
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wire adc_pn_match_i1_s;
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wire adc_pn_match_i1_z_s;
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wire adc_pn_match_i1_d_s;
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wire [23:0] adc_pn_data_i1_s;
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wire [23:0] adc_data_in_q1_s;
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wire adc_pn_err_q1_s;
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wire adc_pn_update_q1_s;
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wire adc_pn_match_q1_s;
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wire adc_pn_match_q1_z_s;
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wire adc_pn_match_q1_d_s;
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wire [23:0] adc_pn_data_q1_s;
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wire [23:0] adc_data_in_i2_s;
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wire adc_pn_err_i2_s;
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wire adc_pn_update_i2_s;
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wire adc_pn_match_i2_s;
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wire adc_pn_match_i2_z_s;
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wire adc_pn_match_i2_d_s;
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wire [23:0] adc_pn_data_i2_s;
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wire [23:0] adc_data_in_q2_s;
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wire adc_pn_err_q2_s;
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wire adc_pn_update_q2_s;
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wire adc_pn_match_q2_s;
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wire adc_pn_match_q2_z_s;
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wire adc_pn_match_q2_d_s;
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wire [23:0] adc_pn_data_q2_s;
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// prbs-9 function
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function [23:0] pn09;
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input [23:0] din;
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reg [23:0] dout;
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begin
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dout[23] = din[ 8] ^ din[ 4];
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dout[22] = din[ 7] ^ din[ 3];
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dout[21] = din[ 6] ^ din[ 2];
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dout[20] = din[ 5] ^ din[ 1];
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dout[19] = din[ 4] ^ din[ 0];
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dout[18] = din[ 3] ^ din[ 8] ^ din[ 4];
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dout[17] = din[ 2] ^ din[ 7] ^ din[ 3];
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dout[16] = din[ 1] ^ din[ 6] ^ din[ 2];
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dout[15] = din[ 0] ^ din[ 5] ^ din[ 1];
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dout[14] = din[ 8] ^ din[ 0];
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dout[13] = din[ 7] ^ din[ 8] ^ din[ 4];
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dout[12] = din[ 6] ^ din[ 7] ^ din[ 3];
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dout[11] = din[ 5] ^ din[ 6] ^ din[ 2];
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dout[10] = din[ 4] ^ din[ 5] ^ din[ 1];
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dout[ 9] = din[ 3] ^ din[ 4] ^ din[ 0];
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dout[ 8] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
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dout[ 7] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
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dout[ 6] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
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dout[ 5] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
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dout[ 4] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
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dout[ 3] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
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dout[ 2] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
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dout[ 1] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
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dout[ 0] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
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pn09 = dout;
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end
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endfunction
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// prbs-11 function
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function [23:0] pn11;
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input [23:0] din;
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reg [23:0] dout;
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begin
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dout[23] = din[10] ^ din[ 8];
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dout[22] = din[ 9] ^ din[ 7];
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dout[21] = din[ 8] ^ din[ 6];
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dout[20] = din[ 7] ^ din[ 5];
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dout[19] = din[ 6] ^ din[ 4];
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dout[18] = din[ 5] ^ din[ 3];
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dout[17] = din[ 4] ^ din[ 2];
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dout[16] = din[ 3] ^ din[ 1];
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dout[15] = din[ 2] ^ din[ 0];
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dout[14] = din[ 1] ^ din[10] ^ din[ 8];
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dout[13] = din[ 0] ^ din[ 9] ^ din[ 7];
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dout[12] = din[10] ^ din[ 6];
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dout[11] = din[ 9] ^ din[ 5];
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dout[10] = din[ 8] ^ din[ 4];
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dout[ 9] = din[ 7] ^ din[ 3];
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dout[ 8] = din[ 6] ^ din[ 2];
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dout[ 7] = din[ 5] ^ din[ 1];
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dout[ 6] = din[ 4] ^ din[ 0];
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dout[ 5] = din[ 3] ^ din[10] ^ din[ 8];
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dout[ 4] = din[ 2] ^ din[ 9] ^ din[ 7];
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dout[ 3] = din[ 1] ^ din[ 8] ^ din[ 6];
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dout[ 2] = din[ 0] ^ din[ 7] ^ din[ 5];
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dout[ 1] = din[10] ^ din[ 6] ^ din[ 8] ^ din[ 4];
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dout[ 0] = din[ 9] ^ din[ 5] ^ din[ 7] ^ din[ 3];
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pn11 = dout;
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end
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endfunction
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// prbs-15 function
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function [23:0] pn15;
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input [23:0] din;
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reg [23:0] dout;
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begin
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dout[23] = din[14] ^ din[13];
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dout[22] = din[13] ^ din[12];
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dout[21] = din[12] ^ din[11];
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dout[20] = din[11] ^ din[10];
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dout[19] = din[10] ^ din[ 9];
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dout[18] = din[ 9] ^ din[ 8];
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dout[17] = din[ 8] ^ din[ 7];
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dout[16] = din[ 7] ^ din[ 6];
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dout[15] = din[ 6] ^ din[ 5];
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dout[14] = din[ 5] ^ din[ 4];
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dout[13] = din[ 4] ^ din[ 3];
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dout[12] = din[ 3] ^ din[ 2];
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dout[11] = din[ 2] ^ din[ 1];
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dout[10] = din[ 1] ^ din[ 0];
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dout[ 9] = din[ 0] ^ din[14] ^ din[13];
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dout[ 8] = din[14] ^ din[12];
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dout[ 7] = din[13] ^ din[11];
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dout[ 6] = din[12] ^ din[10];
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dout[ 5] = din[11] ^ din[ 9];
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dout[ 4] = din[10] ^ din[ 8];
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dout[ 3] = din[ 9] ^ din[ 7];
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dout[ 2] = din[ 8] ^ din[ 6];
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dout[ 1] = din[ 7] ^ din[ 5];
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dout[ 0] = din[ 6] ^ din[ 4];
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pn15 = dout;
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end
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endfunction
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// prbs-20 function
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function [23:0] pn20;
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input [23:0] din;
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reg [23:0] dout;
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begin
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dout[23] = din[19] ^ din[ 2];
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dout[22] = din[18] ^ din[ 1];
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dout[21] = din[17] ^ din[ 0];
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dout[20] = din[16] ^ din[19] ^ din[ 2];
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dout[19] = din[15] ^ din[18] ^ din[ 1];
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dout[18] = din[14] ^ din[17] ^ din[ 0];
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dout[17] = din[13] ^ din[16] ^ din[19] ^ din[ 2];
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dout[16] = din[12] ^ din[15] ^ din[18] ^ din[ 1];
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dout[15] = din[11] ^ din[14] ^ din[17] ^ din[ 0];
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dout[14] = din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
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dout[13] = din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
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dout[12] = din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
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dout[11] = din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
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dout[10] = din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
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dout[ 9] = din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
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dout[ 8] = din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
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dout[ 7] = din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
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dout[ 6] = din[ 2] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
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dout[ 5] = din[ 1] ^ din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
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dout[ 4] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
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dout[ 3] = din[19] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
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dout[ 2] = din[18] ^ din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
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dout[ 1] = din[17] ^ din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
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dout[ 0] = din[16] ^ din[ 2] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
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pn20 = dout;
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end
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endfunction
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// prbs generators run at 24bits wide
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assign dac_valid_t_s = dac_valid_in & dac_valid_t;
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always @(posedge clk) begin
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if (dac_valid_in == 1'b1) begin
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dac_valid_t <= ~dac_valid_t;
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end
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if (dac_pn_enb_i1 == 1'b0) begin
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dac_pn_i1 <= 24'hffffff;
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end else if (dac_valid_t_s == 1'b1) begin
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dac_pn_i1 <= pn09(dac_pn_i1);
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end
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if (dac_pn_enb_q1 == 1'b0) begin
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dac_pn_q1 <= 24'hffffff;
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end else if (dac_valid_t_s == 1'b1) begin
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dac_pn_q1 <= pn11(dac_pn_q1);
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end
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if (dac_pn_enb_i2 == 1'b0) begin
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dac_pn_i2 <= 24'hffffff;
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end else if (dac_valid_t_s == 1'b1) begin
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dac_pn_i2 <= pn15(dac_pn_i2);
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end
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if (dac_pn_enb_q2 == 1'b0) begin
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dac_pn_q2 <= 24'hffffff;
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end else if (dac_valid_t_s == 1'b1) begin
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dac_pn_q2 <= pn20(dac_pn_q2);
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end
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end
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// hold adc data for loopback, it is assumed that there is a one to one mapping
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// of receive and transmit (the rates are the same).
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always @(posedge clk) begin
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if (adc_valid_in == 1'b1) begin
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dac_lb_i1 <= adc_data_in_i1;
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dac_lb_q1 <= adc_data_in_q1;
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dac_lb_i2 <= adc_data_in_i2;
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dac_lb_q2 <= adc_data_in_q2;
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end
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end
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// dac outputs-
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always @(posedge clk) begin
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dac_valid <= dac_valid_in;
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if (dac_pn_enb_i1 == 1'b1) begin
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if (dac_valid_t == 1'b1) begin
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dac_data_i1 <= dac_pn_i1[11:0];
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end else begin
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dac_data_i1 <= dac_pn_i1[23:12];
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end
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end else if (dac_lb_enb_i1 == 1'b1) begin
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dac_data_i1 <= dac_lb_i1;
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end else begin
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dac_data_i1 <= dac_data_in_i1;
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|
end
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if (dac_pn_enb_q1 == 1'b1) begin
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if (dac_valid_t == 1'b1) begin
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dac_data_q1 <= dac_pn_q1[11:0];
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end else begin
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dac_data_q1 <= dac_pn_q1[23:12];
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|
end
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end else if (dac_lb_enb_q1 == 1'b1) begin
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dac_data_q1 <= dac_lb_q1;
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end else begin
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dac_data_q1 <= dac_data_in_q1;
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end
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if (dac_pn_enb_i2 == 1'b1) begin
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if (dac_valid_t == 1'b1) begin
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|
dac_data_i2 <= dac_pn_i2[11:0];
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end else begin
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dac_data_i2 <= dac_pn_i2[23:12];
|
|
end
|
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end else if (dac_lb_enb_i2 == 1'b1) begin
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dac_data_i2 <= dac_lb_i2;
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|
end else begin
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|
dac_data_i2 <= dac_data_in_i2;
|
|
end
|
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if (dac_pn_enb_q2 == 1'b1) begin
|
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if (dac_valid_t == 1'b1) begin
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|
dac_data_q2 <= dac_pn_q2[11:0];
|
|
end else begin
|
|
dac_data_q2 <= dac_pn_q2[23:12];
|
|
end
|
|
end else if (dac_lb_enb_q2 == 1'b1) begin
|
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dac_data_q2 <= dac_lb_q2;
|
|
end else begin
|
|
dac_data_q2 <= dac_data_in_q2;
|
|
end
|
|
end
|
|
|
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// adc pn monitoring
|
|
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assign adc_valid_t_s = adc_valid_in & adc_valid_t;
|
|
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assign adc_data_in_i1_s = {adc_data_in_i1_d, adc_data_in_i1};
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assign adc_pn_err_i1_s = ~(adc_pn_oos_i1 | adc_pn_match_i1_s);
|
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assign adc_pn_update_i1_s = ~(adc_pn_oos_i1 ^ adc_pn_match_i1_s);
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assign adc_pn_match_i1_s = adc_pn_match_i1_d_s & adc_pn_match_i1_z_s;
|
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assign adc_pn_match_i1_z_s = (adc_data_in_i1_s == 24'd0) ? 1'b0 : 1'b1;
|
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assign adc_pn_match_i1_d_s = (adc_data_in_i1_s == adc_pn_data_i1) ? 1'b1 : 1'b0;
|
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assign adc_pn_data_i1_s = (adc_pn_oos_i1 == 1'b1) ? adc_data_in_i1_s : adc_pn_data_i1;
|
|
|
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assign adc_data_in_q1_s = {adc_data_in_q1_d, adc_data_in_q1};
|
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assign adc_pn_err_q1_s = ~(adc_pn_oos_q1 | adc_pn_match_q1_s);
|
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assign adc_pn_update_q1_s = ~(adc_pn_oos_q1 ^ adc_pn_match_q1_s);
|
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assign adc_pn_match_q1_s = adc_pn_match_q1_d_s & adc_pn_match_q1_z_s;
|
|
assign adc_pn_match_q1_z_s = (adc_data_in_q1_s == 24'd0) ? 1'b0 : 1'b1;
|
|
assign adc_pn_match_q1_d_s = (adc_data_in_q1_s == adc_pn_data_q1) ? 1'b1 : 1'b0;
|
|
assign adc_pn_data_q1_s = (adc_pn_oos_q1 == 1'b1) ? adc_data_in_q1_s : adc_pn_data_q1;
|
|
|
|
assign adc_data_in_i2_s = {adc_data_in_i2_d, adc_data_in_i2};
|
|
assign adc_pn_err_i2_s = ~(adc_pn_oos_i2 | adc_pn_match_i2_s);
|
|
assign adc_pn_update_i2_s = ~(adc_pn_oos_i2 ^ adc_pn_match_i2_s);
|
|
assign adc_pn_match_i2_s = adc_pn_match_i2_d_s & adc_pn_match_i2_z_s;
|
|
assign adc_pn_match_i2_z_s = (adc_data_in_i2_s == 24'd0) ? 1'b0 : 1'b1;
|
|
assign adc_pn_match_i2_d_s = (adc_data_in_i2_s == adc_pn_data_i2) ? 1'b1 : 1'b0;
|
|
assign adc_pn_data_i2_s = (adc_pn_oos_i2 == 1'b1) ? adc_data_in_i2_s : adc_pn_data_i2;
|
|
|
|
assign adc_data_in_q2_s = {adc_data_in_q2_d, adc_data_in_q2};
|
|
assign adc_pn_err_q2_s = ~(adc_pn_oos_q2 | adc_pn_match_q2_s);
|
|
assign adc_pn_update_q2_s = ~(adc_pn_oos_q2 ^ adc_pn_match_q2_s);
|
|
assign adc_pn_match_q2_s = adc_pn_match_q2_d_s & adc_pn_match_q2_z_s;
|
|
assign adc_pn_match_q2_z_s = (adc_data_in_q2_s == 24'd0) ? 1'b0 : 1'b1;
|
|
assign adc_pn_match_q2_d_s = (adc_data_in_q2_s == adc_pn_data_q2) ? 1'b1 : 1'b0;
|
|
assign adc_pn_data_q2_s = (adc_pn_oos_q2 == 1'b1) ? adc_data_in_q2_s : adc_pn_data_q2;
|
|
|
|
// adc pn running sequence
|
|
|
|
always @(posedge clk) begin
|
|
if (adc_valid_in == 1'b1) begin
|
|
adc_valid_t <= ~adc_valid_t;
|
|
adc_data_in_i1_d <= adc_data_in_i1;
|
|
adc_data_in_q1_d <= adc_data_in_q1;
|
|
adc_data_in_i2_d <= adc_data_in_i2;
|
|
adc_data_in_q2_d <= adc_data_in_q2;
|
|
end
|
|
if (adc_valid_t_s == 1'b1) begin
|
|
adc_pn_data_i1 <= pn09(adc_pn_data_i1_s);
|
|
adc_pn_data_q1 <= pn11(adc_pn_data_q1_s);
|
|
adc_pn_data_i2 <= pn15(adc_pn_data_i2_s);
|
|
adc_pn_data_q2 <= pn20(adc_pn_data_q2_s);
|
|
end
|
|
end
|
|
|
|
// pn oos and counters (16 to clear and set).
|
|
|
|
always @(posedge clk) begin
|
|
if (adc_valid_t_s == 1'b1) begin
|
|
adc_pn_err_i1 <= adc_pn_err_i1_s;
|
|
if ((adc_pn_update_i1_s == 1'b1) && (adc_pn_oos_count_i1 >= 15)) begin
|
|
adc_pn_oos_i1 <= ~adc_pn_oos_i1;
|
|
end
|
|
if (adc_pn_update_i1_s == 1'b1) begin
|
|
adc_pn_oos_count_i1 <= adc_pn_oos_count_i1 + 1'b1;
|
|
end else begin
|
|
adc_pn_oos_count_i1 <= 'd0;
|
|
end
|
|
adc_pn_err_q1 <= adc_pn_err_q1_s;
|
|
if ((adc_pn_update_q1_s == 1'b1) && (adc_pn_oos_count_q1 >= 15)) begin
|
|
adc_pn_oos_q1 <= ~adc_pn_oos_q1;
|
|
end
|
|
if (adc_pn_update_q1_s == 1'b1) begin
|
|
adc_pn_oos_count_q1 <= adc_pn_oos_count_q1 + 1'b1;
|
|
end else begin
|
|
adc_pn_oos_count_q1 <= 'd0;
|
|
end
|
|
adc_pn_err_i2 <= adc_pn_err_i2_s;
|
|
if ((adc_pn_update_i2_s == 1'b1) && (adc_pn_oos_count_i2 >= 15)) begin
|
|
adc_pn_oos_i2 <= ~adc_pn_oos_i2;
|
|
end
|
|
if (adc_pn_update_i2_s == 1'b1) begin
|
|
adc_pn_oos_count_i2 <= adc_pn_oos_count_i2 + 1'b1;
|
|
end else begin
|
|
adc_pn_oos_count_i2 <= 'd0;
|
|
end
|
|
adc_pn_err_q2 <= adc_pn_err_q2_s;
|
|
if ((adc_pn_update_q2_s == 1'b1) && (adc_pn_oos_count_q2 >= 15)) begin
|
|
adc_pn_oos_q2 <= ~adc_pn_oos_q2;
|
|
end
|
|
if (adc_pn_update_q2_s == 1'b1) begin
|
|
adc_pn_oos_count_q2 <= adc_pn_oos_count_q2 + 1'b1;
|
|
end else begin
|
|
adc_pn_oos_count_q2 <= 'd0;
|
|
end
|
|
end
|
|
end
|
|
|
|
endmodule
|
|
|
|
// ***************************************************************************
|
|
// ***************************************************************************
|