Adrian Costina f51871c1e4 axi_ad9144: Updated altera interfaces, added FIFO conduits per channel		2015-11-24 11:44:07 +02:00
..
Makefile	Makefiles: Updated Makefiles	2015-10-23 10:44:27 +03:00
axi_ad9144.v	hdl/library: Update the IP parameters	2015-08-19 14:11:47 +03:00
axi_ad9144_channel.v	hdl/library: Update the IP parameters	2015-08-19 14:11:47 +03:00
axi_ad9144_constr.xdc	axi_ad9144: Added CDC and reset constraints	2015-04-23 10:19:43 +03:00
axi_ad9144_core.v	axi_ad9144: Clock ratio is indicating a sampling clock ratio	2015-09-24 11:18:48 +03:00
axi_ad9144_hw.tcl	axi_ad9144: Updated altera interfaces, added FIFO conduits per channel	2015-11-24 11:44:07 +02:00
axi_ad9144_if.v	Add .gitattributes file	2015-06-26 11:07:10 +02:00
axi_ad9144_ip.tcl	ad9144- ip updates	2015-09-30 11:37:10 -04:00