151 lines
5.5 KiB
Verilog
151 lines
5.5 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// This is the dac physical interface (drives samples from the low speed clock to the
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// dac clock domain.
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`timescale 1ns/100ps
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module axi_ad9144_if (
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// jesd interface
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// tx_clk is (line-rate/40)
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tx_clk,
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tx_data,
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// dac interface
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dac_clk,
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dac_rst,
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dac_data_0_0,
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dac_data_0_1,
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dac_data_0_2,
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dac_data_0_3,
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dac_data_1_0,
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dac_data_1_1,
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dac_data_1_2,
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dac_data_1_3,
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dac_data_2_0,
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dac_data_2_1,
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dac_data_2_2,
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dac_data_2_3,
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dac_data_3_0,
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dac_data_3_1,
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dac_data_3_2,
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dac_data_3_3);
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// jesd interface
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// tx_clk is (line-rate/40)
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input tx_clk;
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output [255:0] tx_data;
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// dac interface
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output dac_clk;
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input dac_rst;
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input [15:0] dac_data_0_0;
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input [15:0] dac_data_0_1;
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input [15:0] dac_data_0_2;
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input [15:0] dac_data_0_3;
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input [15:0] dac_data_1_0;
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input [15:0] dac_data_1_1;
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input [15:0] dac_data_1_2;
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input [15:0] dac_data_1_3;
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input [15:0] dac_data_2_0;
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input [15:0] dac_data_2_1;
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input [15:0] dac_data_2_2;
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input [15:0] dac_data_2_3;
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input [15:0] dac_data_3_0;
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input [15:0] dac_data_3_1;
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input [15:0] dac_data_3_2;
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input [15:0] dac_data_3_3;
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// internal registers
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reg [255:0] tx_data = 'd0;
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// reorder data for the jesd links
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assign dac_clk = tx_clk;
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always @(posedge dac_clk) begin
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if (dac_rst == 1'b1) begin
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tx_data <= 256'd0;
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end else begin
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tx_data[255:248] <= dac_data_3_3[ 7: 0];
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tx_data[247:240] <= dac_data_3_2[ 7: 0];
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tx_data[239:232] <= dac_data_3_1[ 7: 0];
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tx_data[231:224] <= dac_data_3_0[ 7: 0];
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tx_data[223:216] <= dac_data_3_3[15: 8];
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tx_data[215:208] <= dac_data_3_2[15: 8];
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tx_data[207:200] <= dac_data_3_1[15: 8];
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tx_data[199:192] <= dac_data_3_0[15: 8];
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tx_data[191:184] <= dac_data_2_3[ 7: 0];
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tx_data[183:176] <= dac_data_2_2[ 7: 0];
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tx_data[175:168] <= dac_data_2_1[ 7: 0];
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tx_data[167:160] <= dac_data_2_0[ 7: 0];
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tx_data[159:152] <= dac_data_2_3[15: 8];
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tx_data[151:144] <= dac_data_2_2[15: 8];
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tx_data[143:136] <= dac_data_2_1[15: 8];
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tx_data[135:128] <= dac_data_2_0[15: 8];
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tx_data[127:120] <= dac_data_1_3[ 7: 0];
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tx_data[119:112] <= dac_data_1_2[ 7: 0];
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tx_data[111:104] <= dac_data_1_1[ 7: 0];
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tx_data[103: 96] <= dac_data_1_0[ 7: 0];
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tx_data[ 95: 88] <= dac_data_1_3[15: 8];
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tx_data[ 87: 80] <= dac_data_1_2[15: 8];
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tx_data[ 79: 72] <= dac_data_1_1[15: 8];
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tx_data[ 71: 64] <= dac_data_1_0[15: 8];
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tx_data[ 63: 56] <= dac_data_0_3[ 7: 0];
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tx_data[ 55: 48] <= dac_data_0_2[ 7: 0];
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tx_data[ 47: 40] <= dac_data_0_1[ 7: 0];
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tx_data[ 39: 32] <= dac_data_0_0[ 7: 0];
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tx_data[ 31: 24] <= dac_data_0_3[15: 8];
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tx_data[ 23: 16] <= dac_data_0_2[15: 8];
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tx_data[ 15: 8] <= dac_data_0_1[15: 8];
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tx_data[ 7: 0] <= dac_data_0_0[15: 8];
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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