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Laszlo Nagy 6ef803e7ab jesd204: Make character replacement opt in feature 
In order to keep resource utilization low and for better timing closure
allow disabling of the character replacement logic.

If the parameter is set the frame alignment monitoring is limited to links
where scrambling is on.
 		2021-02-05 15:24:15 +02:00
..
ad_ip_jesd204_tpl_adc ad_ip_jesd204_tpl: Extend valid attribute ranges 2020-10-26 18:12:14 +02:00
ad_ip_jesd204_tpl_common ad_ip_jesd204_tpl_dac: expand address space to accomodate 64 channels 2020-08-11 10:37:59 +03:00
ad_ip_jesd204_tpl_dac ad_ip_jesd204_tpl_dac: added xbar for user channels (dma data) 2020-11-27 09:45:11 +02:00
axi_jesd204_common jesd204: Add support for 8-byte JESD204B, frame alignment character insertion/replacement 2021-02-05 15:24:15 +02:00
axi_jesd204_rx jesd204: Fixed TX frame mark timing. Added start and end of multiframe signals as RX and TX ports 2021-02-05 15:24:15 +02:00
axi_jesd204_tx jesd204: Fixed TX frame mark timing. Added start and end of multiframe signals as RX and TX ports 2021-02-05 15:24:15 +02:00
interfaces jesd204: Add support for 8-byte JESD204B, frame alignment character insertion/replacement 2021-02-05 15:24:15 +02:00
jesd204_common jesd204: Make character replacement opt in feature 2021-02-05 15:24:15 +02:00
jesd204_rx jesd204: Make character replacement opt in feature 2021-02-05 15:24:15 +02:00
jesd204_rx_static_config jesd204: Add support for 8-byte JESD204B, frame alignment character insertion/replacement 2021-02-05 15:24:15 +02:00
jesd204_soft_pcs_rx jesd204: Clean-up combinatorial logic 2020-09-29 17:27:42 +03:00
jesd204_soft_pcs_tx jesd204: Clean-up combinatorial logic 2020-09-29 17:27:42 +03:00
jesd204_tx jesd204: Make character replacement opt in feature 2021-02-05 15:24:15 +02:00
jesd204_tx_static_config jesd204: Add support for 8-byte JESD204B, frame alignment character insertion/replacement 2021-02-05 15:24:15 +02:00
scripts jesd204: DAC TPL to support 64 channels 2020-08-11 10:37:59 +03:00
tb jesd204: Add support for 8-byte JESD204B, frame alignment character insertion/replacement 2021-02-05 15:24:15 +02:00
README.md jesd204: update README to reflect rev C 2020-06-23 13:52:35 +03:00

README.md

Analog Devices JESD204B HDL Support

Licensing

The ADI JESD204 Core is released under the following license, which is different than all other HDL cores in this repository.

Please read this, and understand the freedoms and responsibilities you have by using this source code/core.

The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.

This core is free software, you can use run, copy, study, change, ask questions about and improve this core. Distribution of source, or resulting binaries (including those inside an FPGA or ASIC) require you to release the source of the entire project (excluding the system libraries provide by the tools/compiler/FPGA vendor). These are the terms of the GNU General Public License version 2 as published by the Free Software Foundation.

This core is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.

You should have received a copy of the GNU General Public License version 2 along with this source code, and binary. If not, see http://www.gnu.org/licenses/.

Commercial licenses (with commercial support) of this JESD204 core are also available under terms different than the General Public License. (e.g. they do not require you to accompany any image (FPGA or ASIC) using the JESD204 core with any corresponding source code.) For these alternate terms you must purchase a license from Analog Devices Technology Licensing Office. Users interested in such a license should contact jesd204-licensing@analog.com for more information. This commercial license is sub-licensable (if you purchase chips from Analog Devices, incorporate them into your PCB level product, and purchase a JESD204 license, end users of your product will also have a license to use this core in a commercial setting without releasing their source code).

In addition, we kindly ask you to acknowledge ADI in any program, application or publication in which you use this JESD204 HDL core. (You are not required to do so; it is up to your common sense to decide whether you want to comply with this request or not.) For general publications, we suggest referencing : “The design and implementation of the JESD204 HDL Core used in this project is copyright © 2016-2017, Analog Devices, Inc.”

Support

Analog Devices will provide limited online support for anyone using the core with Analog Devices components (ADC, DAC, Clock, etc) via https://ez.analog.com/community/fpga under the GPL license. If you would like deterministic support when using this core with an ADI component, please investigate a commercial license. Using a non-ADI JESD204 device with this core is possible under the GPL, but Analog Devices will not help with issues you may encounter.

Documenation