203 lines
7.6 KiB
Tcl
Executable File
203 lines
7.6 KiB
Tcl
Executable File
#
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# The ADI JESD204 Core is released under the following license, which is
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# different than all other HDL cores in this repository.
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#
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# Please read this, and understand the freedoms and responsibilities you have
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# by using this source code/core.
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#
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# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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#
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# This core is free software, you can use run, copy, study, change, ask
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# questions about and improve this core. Distribution of source, or resulting
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# binaries (including those inside an FPGA or ASIC) require you to release the
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# source of the entire project (excluding the system libraries provide by the
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# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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# License version 2 as published by the Free Software Foundation.
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#
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# This core is distributed in the hope that it will be useful, but WITHOUT ANY
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# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License version 2
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# along with this source code, and binary. If not, see
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# <http://www.gnu.org/licenses/>.
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#
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# Commercial licenses (with commercial support) of this JESD204 core are also
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# available under terms different than the General Public License. (e.g. they
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# do not require you to accompany any image (FPGA or ASIC) using the JESD204
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# core with any corresponding source code.) For these alternate terms you must
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# purchase a license from Analog Devices Technology Licensing Office. Users
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# interested in such a license should contact jesd204-licensing@analog.com for
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# more information. This commercial license is sub-licensable (if you purchase
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# chips from Analog Devices, incorporate them into your PCB level product, and
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# purchase a JESD204 license, end users of your product will also have a
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# license to use this core in a commercial setting without releasing their
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# source code).
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#
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# In addition, we kindly ask you to acknowledge ADI in any program, application
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# or publication in which you use this JESD204 HDL core. (You are not required
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# to do so; it is up to your common sense to decide whether you want to comply
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# with this request or not.) For general publications, we suggest referencing :
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# “The design and implementation of the JESD204 HDL Core used in this project
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# is copyright © 2016-2017, Analog Devices, Inc.”
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#
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
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adi_ip_create jesd204_rx
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adi_ip_files jesd204_rx [list \
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"jesd204_rx_lane.v" \
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"jesd204_rx_lane_64b.v" \
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"jesd204_rx_header.v" \
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"jesd204_rx_cgs.v" \
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"jesd204_rx_ctrl.v" \
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"jesd204_rx_ctrl_64b.v" \
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"elastic_buffer.v" \
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"error_monitor.v" \
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"jesd204_ilas_monitor.v" \
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"align_mux.v" \
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"jesd204_lane_latency_monitor.v" \
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"jesd204_rx_frame_align.v" \
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"jesd204_rx_constr.ttcl" \
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"jesd204_rx.v" \
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]
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adi_ip_properties_lite jesd204_rx
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adi_ip_ttcl jesd204_rx "jesd204_rx_constr.ttcl"
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adi_ip_add_core_dependencies { \
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analog.com:user:jesd204_common:1.0 \
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}
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set_property display_name "ADI JESD204 Receive" [ipx::current_core]
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set_property description "ADI JESD204 Receive" [ipx::current_core]
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#adi_add_bus "rx_data" "master" \
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# "xilinx.com:interface:axis_rtl:1.0" \
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# "xilinx.com:interface:axis:1.0" \
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# { \
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# { "rx_valid" "TVALID" } \
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# { "rx_data" "TDATA" } \
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# }
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adi_add_multi_bus 16 "rx_phy" "slave" \
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"xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0" \
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"xilinx.com:display_jesd204:jesd204_rx_bus:1.0" \
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[list \
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{ "phy_data" "rxdata" 32 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')) * 8)"} \
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{ "phy_charisk" "rxcharisk" 4 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')))"} \
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{ "phy_disperr" "rxdisperr" 4 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')))"} \
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{ "phy_notintable" "rxnotintable" 4 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')))"} \
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{ "phy_header" "rxheader" 2} \
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{ "phy_block_sync" "rxblock_sync" 1} \
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] \
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"(spirit:decode(id('MODELPARAM_VALUE.NUM_LANES')) > {i})"
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adi_add_bus "rx_cfg" "slave" \
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"analog.com:interface:jesd204_rx_cfg_rtl:1.0" \
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"analog.com:interface:jesd204_rx_cfg:1.0" \
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{ \
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{ "cfg_lanes_disable" "lanes_disable" } \
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{ "cfg_links_disable" "links_disable" } \
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{ "cfg_octets_per_multiframe" "octets_per_multiframe" } \
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{ "cfg_octets_per_frame" "octets_per_frame" } \
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{ "cfg_lmfc_offset" "lmfc_offset" } \
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{ "cfg_sysref_oneshot" "sysref_oneshot" } \
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{ "cfg_sysref_disable" "sysref_disable" } \
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{ "cfg_buffer_delay" "buffer_delay" } \
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{ "cfg_buffer_early_release" "buffer_early_release" } \
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{ "cfg_disable_char_replacement" "disable_char_replacement" } \
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{ "ctrl_err_statistics_reset" "err_statistics_reset" } \
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{ "ctrl_err_statistics_mask" "err_statistics_mask" } \
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{ "cfg_disable_scrambler" "disable_scrambler" } \
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{ "cfg_frame_align_err_threshold" "frame_align_err_threshold" } \
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}
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adi_add_bus "rx_status" "master" \
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"analog.com:interface:jesd204_rx_status_rtl:1.0" \
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"analog.com:interface:jesd204_rx_status:1.0" \
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{ \
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{ "status_ctrl_state" "ctrl_state" } \
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{ "status_lane_cgs_state" "lane_cgs_state" } \
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{ "status_lane_emb_state" "lane_emb_state" } \
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{ "status_err_statistics_cnt" "err_statistics_cnt" } \
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{ "status_lane_ifs_ready" "lane_ifs_ready" } \
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{ "status_lane_latency" "lane_latency" } \
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{ "status_lane_frame_align_err_cnt" "lane_frame_align_err_cnt" } \
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}
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adi_add_bus "rx_ilas_config" "master" \
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"analog.com:interface:jesd204_rx_ilas_config_rtl:1.0" \
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"analog.com:interface:jesd204_rx_ilas_config:1.0" \
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{ \
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{ "ilas_config_valid" "valid" } \
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{ "ilas_config_addr" "addr" } \
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{ "ilas_config_data" "data" } \
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}
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adi_add_bus "rx_event" "master" \
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"analog.com:interface:jesd204_rx_event_rtl:1.0" \
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"analog.com:interface:jesd204_rx_event:1.0" \
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{ \
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{ "event_sysref_alignment_error" "sysref_alignment_error" } \
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{ "event_sysref_edge" "sysref_edge" } \
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{ "event_frame_alignment_error" "frame_alignment_error" } \
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{ "event_unexpected_lane_state_error" "unexpected_lane_state_error" } \
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}
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adi_add_bus_clock "clk" "rx_cfg:rx_ilas_config:rx_event:rx_status:rx_data" "reset"
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adi_set_bus_dependency "rx_ilas_config" "rx_ilas_config" \
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"(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
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adi_set_ports_dependency "sync" \
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"(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
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adi_set_ports_dependency "phy_en_char_align" \
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"(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
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set cc [ipx::current_core]
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set_property -dict [list \
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driver_value 0 \
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] [ipx::get_ports phy_header -of_objects $cc]
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# Arrange GUI page layout
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set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
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# Link layer mode
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set p [ipgui::get_guiparamspec -name "LINK_MODE" -component $cc]
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ipgui::move_param -component $cc -order 0 $p -parent $page0
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set_property -dict [list \
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"display_name" "Link Layer mode" \
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"tooltip" "Link Layer mode" \
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"widget" "comboBox" \
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] $p
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set_property -dict [list \
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value_validation_type pairs \
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value_validation_pairs {64B66B 2 8B10B 1} \
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] [ipx::get_user_parameters $p -of_objects $cc]
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# Data width selection
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set param [ipx::get_user_parameters DATA_PATH_WIDTH -of_objects $cc]
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set_property -dict [list \
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enablement_tcl_expr {$LINK_MODE==1} \
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value_tcl_expr {expr $LINK_MODE*4} \
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] $param
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set param [ipx::add_user_parameter SYSREF_IOB $cc]
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set_property -dict {value_resolve_type user value_format bool value true} $param
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set param [ipgui::add_param -name {SYSREF_IOB} -component $cc -parent $page0]
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set_property -dict [list \
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display_name {Place SYSREF in IOB} \
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widget {checkBox} \
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show_label true \
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] $param
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ipx::create_xgui_files [ipx::current_core]
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ipx::save_core [ipx::current_core]
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