ef278e1c88
Replaced the existing axi_tdd with the new version * Added DEFAULT_POLARITY synth parameter and RO register * Added TDD_STATUS register * Added TDD_SYNC_RST feature * Used the asy_ prefix for signals which are not synced * Added logic to force the state from ARMED to RUNNING when startup_delay=0 * Added feature to finish the burst when the module is disabled before its completion Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com> |
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| .. | ||
| scripts | ||
| Makefile | ||
| axi_tdd.sv | ||
| axi_tdd_channel.sv | ||
| axi_tdd_constr.sdc | ||
| axi_tdd_constr.ttcl | ||
| axi_tdd_counter.sv | ||
| axi_tdd_hw.tcl | ||
| axi_tdd_ip.tcl | ||
| axi_tdd_pkg.sv | ||
| axi_tdd_regmap.sv | ||
| axi_tdd_sync_gen.sv | ||