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Bogdan Luncan 72313df81f Updated the makefiles to build the projects in subdirectories based on the build parameters. 
Running 'make' will build the default project directly in the project folder (like it did before)
Running 'make RX_LANE_RATE=15 TX_LANE_RATE=15' will build the project inside the 'RXRATE15_TXRATE15' subdirectory.
Running 'make CFG=cfg/test_config.txt" will use the variables found inside the configuration file and build the project inside the 'test_config' subdirectory.
Running 'make clean' will clean the default project only.
Running 'make CFG=cfg/test_config.txt clean' will clean the 'testconfig' build.
Running 'make clean-all' will delete all the built configurations and libraries.

Note that the 'JESD' and 'LANE' words from the parameter names are stripped.

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
 		2022-11-14 09:38:42 +02:00
..
Makefile ad4630_fmc: Match project name with folder name 2022-09-26 15:37:49 +03:00
README.md ad463x: Fix readme 2021-10-26 15:42:57 +03:00
system_bd.tcl Updated the makefiles to build the projects in subdirectories based on the build parameters. 2022-11-14 09:38:42 +02:00
system_constr.xdc ad4630_fmc: Initial commit 2021-10-18 16:13:31 +03:00
system_constr_1sdi.xdc ad4630_fmc: Initial commit 2021-10-18 16:13:31 +03:00
system_constr_2sdi.xdc ad4630_fmc: Initial commit 2021-10-18 16:13:31 +03:00
system_constr_4sdi.xdc ad4630_fmc: Initial commit 2021-10-18 16:13:31 +03:00
system_constr_8sdi.xdc ad4630_fmc: Initial commit 2021-10-18 16:13:31 +03:00
system_project.tcl Updated the makefiles to build the projects in subdirectories based on the build parameters. 2022-11-14 09:38:42 +02:00
system_top.v ad4630_fmc: Match project name with folder name 2022-09-26 15:37:49 +03:00

README.md

EVAL-AD463X_FMCZ HDL reference design

Building the design

The design supports almost all the digital interface modes of AD4630-24, a new bit stream should be generated each time when the targeted configuration changes.

Default configuration: generic SPI mode for clocking, 2 lanes per channel, SDR data capture and capture zone 2.

Building attributes

Attribute name Valid values
CLK_MODE 0 - SPI / 1 - Echo-clock or Master clock
NUM_OF_SDI 1 - Interleaved / 2 - 1LPC / 4 - 2LPC / 8 - 4LPC
CAPTURE_ZONE 1 - negedge of BUSY / 2 - next posedge of CNV
DDR_EN 0 - MISO runs on SDR / 1 - MISO runs on DDR

Example: make CLK_MODE=1 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=0

Documentation

https://wiki.analog.com/resources/eval/user-guides/ad463x/hdl