hotoleanudan 1c208c01d6 ad9656:Add reference design for the ad9656 eval board (#494) ... Added reference design for the ad9656 evaluation board coupled with the zcu102 carrier board. The JESD204 communication link that transfers data from the 4 ADCs to the FPGA has the following paramenters : L=4, M=4, S=1, F=2, HD=0, N=16, NP=16. The JESD204 line rate is configured to be 2.5GHz. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>		2020-10-06 09:53:40 +03:00
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ad9656_fmc_bd.tcl	ad9656:Add reference design for the ad9656 eval board (#494)	2020-10-06 09:53:40 +03:00