pluto_hdl_adi/projects/common/a10soc/system_constr.sdc

7 lines
249 B
Plaintext
Executable File

create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
derive_pll_clocks
derive_clock_uncertainty
set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*]